LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature

The MC88921 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The PLL allows the high current, low skew outputs t

文件：106.7 Kbytes 頁(yè)數(shù)：10 Pages

MOTOROLA

摩托羅拉

LOW SKEW CMOS PLL CLOCK DRIVER With Power–Down/Power–Up Feature

The MC88921 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The PLL allows the high current, low skew outputs to

恩XP

LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature

The MC88921 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The PLL allows the high current, low skew outputs t

文件：106.7 Kbytes 頁(yè)數(shù)：10 Pages

MOTOROLA

摩托羅拉

SMD

IDT

上傳：深圳龐田科技有限公司

QFP64

FREESCA

上傳：深圳市振宏微科技有限公司