Octal D Flip-Flop with Clock Enable

The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time be

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Octal D Flip??lop with Clock Enable

The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time be

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OCTAL D FLIP-FLOP WITH CLOCK ENABLE

The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time be

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Octal D Flip-Flop with Clock Enable

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八路 D 型觸發(fā)器，帶時鐘啟用

The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops withindividual D inputs and Q outputs. The common buffered Clock (CP) input loadsall flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup timebefore ? Ideal for Addressable Register Applications\n? Clock Enable for Address and Data Synchronization Applications\n? Eight Edge-Triggered D Flip-Flops\n? Buffered Common Clock\n? Outputs Source/Sink 24 mA\n? See MC74AC273 for Master Reset Version\n? See MC74AC373 for Transparent Latch Version\n? See M;

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Octal D Flip??lop with Clock Enable

The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time be

文件：122.9 Kbytes 頁數(shù)：10 Pages

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Octal D Flip-Flop with Clock Enable

The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time be

文件：111.52 Kbytes 頁數(shù)：12 Pages

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Octal D Flip??lop with Clock Enable

The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time be

文件：122.9 Kbytes 頁數(shù)：10 Pages

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Octal D Flip-Flop with Clock Enable

The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time be

文件：111.52 Kbytes 頁數(shù)：12 Pages

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Octal D Flip??lop with Clock Enable

The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time be

文件：122.9 Kbytes 頁數(shù)：10 Pages

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安森美半導(dǎo)體