12-BIT PARITY TREE

The MC14531B 12–bit parity tree is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. The circuit consists of 12 data–bit inputs (D0 thru D11), and even or odd parity selection input (W) and an output (Q). The parity selection input can be consi

文件：175.5 Kbytes 頁數(shù)：5 Pages

MOTOROLA

摩托羅拉

12-BIT PARITY TREE

The MC14531B 12–bit parity tree is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. The circuit consists of 12 data–bit inputs (D0 thru D11), and even or odd parity selection input (W) and an output (Q). The parity selection input can be consi

文件：175.5 Kbytes 頁數(shù)：5 Pages

MOTOROLA

摩托羅拉

12-BIT PARITY TREE

The MC14531B 12–bit parity tree is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. The circuit consists of 12 data–bit inputs (D0 thru D11), and even or odd parity selection input (W) and an output (Q). The parity selection input can be consi

文件：175.5 Kbytes 頁數(shù)：5 Pages

MOTOROLA

摩托羅拉

12-BIT PARITY TREE

The MC14531B 12–bit parity tree is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. The circuit consists of 12 data–bit inputs (D0 thru D11), and even or odd parity selection input (W) and an output (Q). The parity selection input can be consi

文件：175.5 Kbytes 頁數(shù)：5 Pages

MOTOROLA

摩托羅拉

12-BIT PARITY TREE

恩XP