Quad Transparent Latch

文件：100.81 Kbytes 頁數(shù)：8 Pages

ONSEMI

安森美半導體

Quad Transparent Latch

文件：100.81 Kbytes 頁數(shù)：8 Pages

ONSEMI

安森美半導體

Quad Transparent Latch

文件：100.81 Kbytes 頁數(shù)：8 Pages

ONSEMI

安森美半導體

Quad Transparent Latch

文件：101.21 Kbytes 頁數(shù)：6 Pages

ONSEMI

安森美半導體

Quad Transparent Latch

文件：100.81 Kbytes 頁數(shù)：8 Pages

ONSEMI

安森美半導體

Quad Transparent Latch

文件：101.21 Kbytes 頁數(shù)：6 Pages

ONSEMI

安森美半導體

Quad Transparent Latch

文件：100.81 Kbytes 頁數(shù)：8 Pages

ONSEMI

安森美半導體

Quad Transparent Latch

文件：100.81 Kbytes 頁數(shù)：8 Pages

ONSEMI

安森美半導體

Quad transparent latch

The MC14042B Quad Transparent Latch is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can

恩XP

四路透明鎖存

The MC14042B Quad Transparent Latch is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can ? Buffered Data Inputs\n? Common Clock\n? Clock Polarity Control\n? Q and Qbar Outputs\n? Double Diode Input Protection\n? Supply Voltage Range = 3.0 Vdc to 1 8 Vdc\n? Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range\n? Pb-Free Packages a;

ONSEMI

安森美半導體