首頁(yè) >MC100EPT23>規(guī)格書列表
| 型號(hào) | 下載 訂購(gòu) | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
MC100EPT23 | Clock Management Design Using Low Skew and Low Jitter Devices Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv 文件:209.34 Kbytes 頁(yè)數(shù):8 Pages | ONSEMI 安森美半導(dǎo)體 | ONSEMI | |
MC100EPT23 | Dual Differential LVPECL to LVTTL Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the E 文件:65.069 Kbytes 頁(yè)數(shù):8 Pages | ONSEMI 安森美半導(dǎo)體 | ONSEMI | |
MC100EPT23 | 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator 文件:85.66 Kbytes 頁(yè)數(shù):8 Pages | ONSEMI 安森美半導(dǎo)體 | ONSEMI | |
MC100EPT23 | 轉(zhuǎn)換器,雙路差分 LVPECL 至 LVTTL The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL/LVDS/CML input levels and LVTTL/LVCMOS output levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the EPT23 makes it ideal for applicatio ? 1.5ns Typical Propagation Delay\n? Maximum Operating Frequency > 275MHz\n? 24mA LVTTL Outputs\n? Operating Range: VCC= 3.0 V to 3.6 V with GND = 0 V\n? Open Input Default State\n? Q Output will default LOW with inputs open or at GND\n? Pb-Free Packages are Available; | ONSEMI 安森美半導(dǎo)體 | ONSEMI | |
Dual Differential LVPECL to LVTTL Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the E 文件:65.069 Kbytes 頁(yè)數(shù):8 Pages | ONSEMI 安森美半導(dǎo)體 | ONSEMI | ||
Dual Differential LVPECL to LVTTL Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the E 文件:65.069 Kbytes 頁(yè)數(shù):8 Pages | ONSEMI 安森美半導(dǎo)體 | ONSEMI | ||
Dual Differential LVPECL to LVTTL Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the E 文件:65.069 Kbytes 頁(yè)數(shù):8 Pages | ONSEMI 安森美半導(dǎo)體 | ONSEMI | ||
Dual Differential LVPECL to LVTTL Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the E 文件:65.069 Kbytes 頁(yè)數(shù):8 Pages | ONSEMI 安森美半導(dǎo)體 | ONSEMI | ||
Dual Differential LVPECL to LVTTL Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the E 文件:65.069 Kbytes 頁(yè)數(shù):8 Pages | ONSEMI 安森美半導(dǎo)體 | ONSEMI | ||
Dual Differential LVPECL to LVTTL Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the E 文件:65.069 Kbytes 頁(yè)數(shù):8 Pages | ONSEMI 安森美半導(dǎo)體 | ONSEMI |
技術(shù)參數(shù)
- Pb-free:
Pb
- Halide free:
H
- Status:
Active
- Channels:
2
- Input Level:
CML
- Output Level:
TTL
- VCC Typ (V):
3.3
- fMax Typ (MHz):
350
- tpd Typ (ns):
1.5
- tR & tF Max (ps):
900
- Package Type:
DFN-8
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
原裝 |
25+23+ |
SOP8 |
12940 |
絕對(duì)原裝正品全新進(jìn)口深圳現(xiàn)貨 |
詢價(jià) | ||
ON/安森美 |
23+ |
13000 |
原廠授權(quán)一級(jí)代理,專業(yè)海外優(yōu)勢(shì)訂貨,價(jià)格優(yōu)勢(shì)、品種 |
詢價(jià) | |||
MOTOROLA |
24+ |
SOP |
3000 |
公司現(xiàn)貨 |
詢價(jià) | ||
ON |
SOP8 |
206 |
正品原裝--自家現(xiàn)貨-實(shí)單可談 |
詢價(jià) | |||
ON |
25+ |
TO-247 |
18000 |
原廠直接發(fā)貨進(jìn)口原裝 |
詢價(jià) | ||
MOT |
00+ |
SOP8 |
2445 |
全新原裝進(jìn)口自己庫(kù)存優(yōu)勢(shì) |
詢價(jià) | ||
ON |
23+ |
SSOP |
5000 |
原裝正品,假一罰十 |
詢價(jià) | ||
ONSEMICONDUCTOR |
16+ |
NA |
8800 |
原裝現(xiàn)貨,貨真價(jià)優(yōu) |
詢價(jià) | ||
ON |
24+ |
SOP-8 |
4652 |
公司原廠原裝現(xiàn)貨假一罰十!特價(jià)出售!強(qiáng)勢(shì)庫(kù)存! |
詢價(jià) | ||
ON |
25+ |
SOP-8 |
135 |
百分百原裝正品 真實(shí)公司現(xiàn)貨庫(kù)存 本公司只做原裝 可 |
詢價(jià) |
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