MC100EPT21中文資料LVPECL/LVDS/CML 到 LVTTL/LVCMOS 差分轉(zhuǎn)換器數(shù)據(jù)手冊(cè)O(shè)NSEMI規(guī)格書

描述 Description

The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL/LVDS/CML input levels and LVTTL/LVCMOS output levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal. The VBB output allows the EPT21 to be cap coupled in either single-ended or differential input mode. When single-ended cap coupled, VBB output tied to the D0 input for a non-inverting buffer or the D0 input for an inverting buffer. When cap coupled differentially, VBB output is connected through a resistor to each input pin. If used, the VBB pin should be bypassed to VCC via a 0.01 F capacitor. For additional information see AND8020. For a single-ended direct connection use an external voltage reference source such as a resistor divider. Do not use VBB for a single-ended direct connection.

特性 Features

? 1.4ns Typical Propagation Delay
? Maximum Frequency > 275 MHz Typical
? 24mA TTL outputs
? LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs
? The 100 Series Contains Temperature Compensation
? VBB Output
? New Differential Input Common Mode Range

應(yīng)用 Application

? Precision Clock Translation

簡(jiǎn)介

MC100EPT21屬于集成電路（IC）的轉(zhuǎn)換器電平移位器。由ONSEMI制造生產(chǎn)的MC100EPT21轉(zhuǎn)換器，電平移位器邏輯轉(zhuǎn)換器或電平移位器 IC 可用于在數(shù)字邏輯設(shè)備之間傳遞信息，這些設(shè)備可在不同/不兼容的供電電壓下工作，或可實(shí)現(xiàn)不同的信令方式。例如，可以將需要 5 V 電源的數(shù)字輸出傳感器連接到具有 3.3 V I/O 電源的 FPGA，或者在 CMOS 或 TTL 等單端信令方式與 PECL 或 LVDS 等差分技術(shù)之間進(jìn)行轉(zhuǎn)換。