3.3V ECL Programmable Delay Chip with FTUNE

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3.3V ECL Programmable Delay Chip with FTUNE

文件：215.19 Kbytes 頁數(shù)：18 Pages

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3.3V ECL Programmable Delay Chip with FTUNE

文件：215.19 Kbytes 頁數(shù)：18 Pages

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3.3V ECL Programmable Delay Chip with FTUNE

文件：151.05 Kbytes 頁數(shù)：19 Pages

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安森美半導(dǎo)體

3.3V ECL Programmable Delay Chip with FTUNE

文件：146.25 Kbytes 頁數(shù)：20 Pages

ONSEMI

安森美半導(dǎo)體

3.3V ECL Programmable Delay Chip with FTUNE

文件：215.19 Kbytes 頁數(shù)：18 Pages

ONSEMI

安森美半導(dǎo)體

3.3V ECL Programmable Delay Chip with FTUNE

文件：215.19 Kbytes 頁數(shù)：18 Pages

ONSEMI

安森美半導(dǎo)體

3.3V ECL Programmable Delay Chip with FTUNE

文件：151.05 Kbytes 頁數(shù)：19 Pages

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3.3 V ECL 可編程延遲芯片，帶 FTUNE

The MC100EP196B is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tunability in delay using the FTUNE pin ? Maximum Input Clock Frequency >1.2 GHz Typical\n? Programmable Range: 0 ns to 10 ns\n? Delay Range: 2.2 ns to 12.4 ns\n? 10 ps Increments\n? Linearity 40 ps max\n? PECL Mode Operating Range:VCC = 3.0 V to 3.6 V with VEE = 0 V\n? NECL Mode Operating Range:VCC = 0 V with VEE = 3.0 V to 3.6 V\n? IN/I;

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Package：32-LQFP；包裝：卷帶（TR） 功能：可編程 類別：集成電路（IC） 延遲線 描述：IC DELAY LN 1024TAP PROG 32LQFP

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