3.3V / 5V ECL Quad 2-Input Differential AND/NAND

Description The MC10/100EP105 is a quad 2?input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. The 100 Ser

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3.3V / 5V ECL Quad 2-Input Differential AND/NAND

Description The MC10/100EP105 is a quad 2?input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. The 100 Ser

文件：81.77 Kbytes 頁數(shù)：8 Pages

ONSEMI

安森美半導(dǎo)體

3.3V / 5V ECL Quad 2-Input Differential AND/NAND

Description The MC10/100EP105 is a quad 2?input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. The 100 Ser

文件：81.77 Kbytes 頁數(shù)：8 Pages

ONSEMI

安森美半導(dǎo)體

3.3V / 5V ECL Quad 2-Input Differential AND/NAND

Description The MC10/100EP105 is a quad 2?input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. The 100 Ser

文件：81.77 Kbytes 頁數(shù)：8 Pages

ONSEMI

安森美半導(dǎo)體

3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock

Description The MC10/100EP131 is a Quad Master?slaved D flip?flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring

文件：90.65 Kbytes 頁數(shù)：10 Pages

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3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock

Description The MC10/100EP131 is a Quad Master?slaved D flip?flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring

文件：90.65 Kbytes 頁數(shù)：10 Pages

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3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock

Description The MC10/100EP131 is a Quad Master?slaved D flip?flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring

文件：90.65 Kbytes 頁數(shù)：10 Pages

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Clock Management Design Using Low Skew and Low Jitter Devices

Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv

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?2/4, ?4./5/6 Clock Generation Chip

Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di

文件：140.93 Kbytes 頁數(shù)：8 Pages

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3.3V / 5V ECL /2/4, /4/5/6 Clock Generation Chip

Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di

文件：102.33 Kbytes 頁數(shù)：14 Pages

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