1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9320/MAX9320A are low-skew, 1-to-2 differential drivers designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. Feature

文件：196.72 Kbytes 頁數(shù)：9 Pages

MAXIM

美信

1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

文件：620.61 Kbytes 頁數(shù)：10 Pages

MAXIM

美信

1:2差分LVPECL/LVECL/HSTL時鐘和數(shù)據(jù)驅(qū)動器

MAX9320/MAX9320A是一種低扭曲、1:2差分驅(qū)動器設(shè)計用于時鐘和數(shù)據(jù)分配，由一路輸入再生2路差分輸出。差分輸入經(jīng)過調(diào)整后，可以允許單端輸入，只需外加基準電壓即可。\n\n MAX9320/MAX9320A具有超低傳輸延遲(208ps)、20ps的器件至器件扭曲和6ps的輸出至輸出扭曲以及最大30mA的電源電流等特性，使其尤其適合于時鐘分配。為與差分HSTL和LVPECL信號接口，該器件工作于+2.25V至+3.8V的電源電壓，能夠?qū)崿F(xiàn)在+2.5V或+3.3V標稱電壓系統(tǒng)中，進行高性能的時鐘或數(shù)據(jù)分配。而對于差分LVECL工作方式，該器件工作于-2.25V至-3.8V的電源 ? 改進的MC10LVEP11 (MAX9320)代用產(chǎn)品\n? +2.25V至+3.8V差分HSTL/LVPECL工作方式\n? -2.25V至-3.8V LVECL工作方式\n? 22mA (典型)的低電源電流\n? 20ps (典型)器件至器件扭曲\n? 6ps (典型)輸出至輸出扭曲\n? 208ps (典型)的傳輸延遲\n? 3GHz時最小輸出300mV\n? 輸入開路時，輸出為低電平\n? >2kV的ESD保護(人體模型)\n? 提供熱增強型、底盤裸露的SO封裝;

ADI

亞德諾

1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9320/MAX9320A are low-skew, 1-to-2 differential drivers designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. Feature

文件：196.72 Kbytes 頁數(shù)：9 Pages

MAXIM

美信

1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9320/MAX9320A are low-skew, 1-to-2 differential drivers designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. Feature

文件：196.72 Kbytes 頁數(shù)：9 Pages

MAXIM

美信

1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver

General Description The MAX9320B low-skew, 1-to-2 differential driver is designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. Features ? Impro

文件：120.43 Kbytes 頁數(shù)：7 Pages

MAXIM

美信

1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver

General Description The MAX9320B low-skew, 1-to-2 differential driver is designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. Features ? Impro

文件：120.43 Kbytes 頁數(shù)：7 Pages

MAXIM

美信

1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver

General Description The MAX9320B low-skew, 1-to-2 differential driver is designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. Features ? Impro

文件：120.43 Kbytes 頁數(shù)：7 Pages

MAXIM

美信

1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9320/MAX9320A are low-skew, 1-to-2 differential drivers designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. Feature

文件：196.72 Kbytes 頁數(shù)：9 Pages

MAXIM

美信

1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9320/MAX9320A are low-skew, 1-to-2 differential drivers designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. Feature

文件：196.72 Kbytes 頁數(shù)：9 Pages

MAXIM

美信