Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9312/MAX9314 are low skew, dual 1-to-5 differential drivers designed for clock and data distribution. These devices accept two inputs. Each input is reproduced at five differential outputs. The differential inputs can be adapted to accept single-ended inputs by connecti

文件：112.75 Kbytes 頁(yè)數(shù)：9 Pages

MAXIM

美信

雙路、1:5差分LVPECL/LVECL/HSTL時(shí)鐘和數(shù)據(jù)驅(qū)動(dòng)器

MAX9312/MAX9314是低扭曲、雙路1:5差分驅(qū)動(dòng)器，設(shè)計(jì)用于時(shí)鐘和數(shù)據(jù)分配。這些器件接受兩路輸入。每個(gè)輸入再生5路差分輸出。差分輸入經(jīng)過(guò)調(diào)整后，可以允許單端輸入，只需將片上VBB電源接到一個(gè)輸入端作為參考電壓即可。\nMAX9312/MAX9314具有較低的器件到器件扭曲(30ps)和輸出到輸出扭曲(12ps)，尤其適合于通過(guò)背板或電路板上的時(shí)鐘和數(shù)據(jù)分配。在與差分HSTL和LVPECL信號(hào)接口時(shí)，這些器件工作在+2.25V至+3.8V的電源范圍，能夠?qū)崿F(xiàn)在+2.5V或+3.3V標(biāo)稱電源的系統(tǒng)中，進(jìn)行高性能的時(shí)鐘或數(shù)據(jù)分配。與差分LVECL接口時(shí)，這些器件工作在-2.25V至-3.8

ADI

亞德諾

Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9312/MAX9314 are low skew, dual 1-to-5 differential drivers designed for clock and data distribution. These devices accept two inputs. Each input is reproduced at five differential outputs. The differential inputs can be adapted to accept single-ended inputs by connecti

文件：112.75 Kbytes 頁(yè)數(shù)：9 Pages

MAXIM

美信

Package：32-LQFP；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 時(shí)鐘緩沖器，驅(qū)動(dòng)器 描述：IC CLK BUFFER 1:5

AD

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Package：32-LQFP；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 時(shí)鐘緩沖器，驅(qū)動(dòng)器 描述：IC CLK BUFFER 1:5

AD

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