Ultra Low-Power, Low-Cost Comparators with 2eference

General Description The MAX931-MAX934 single, dual, and quad micropower, low-voltage comparators plus an on-board 2 accurate reference feature the lowest power consumption available. These comparators draw less than 4μA supply current over temperature (MAX931), and include an internal 1.182V ±2 v

文件：164.51 Kbytes 頁數(shù)：16 Pages

MAXIM

美信

超低功耗、低成本比較器、內(nèi)置2%電壓基準(zhǔn)

MAX931–MAX934單通道、雙通道和四通道微功耗低壓比較器加上2%板載精準(zhǔn)基準(zhǔn)電壓源可提供超低功耗。這些比較器在整個(gè)溫度范圍內(nèi)的電源電流消耗小于4μA(MAX931)，并具有1.182V ±2%內(nèi)部基準(zhǔn)電壓、可編程遲滯以及可進(jìn)行灌電流和拉電流操作的TTL/CMOS輸出。\n\n MAX931–MAX934采用+2.5V至+11V單電源（或±1.25V至±5V雙電源）工作，每個(gè)比較器的輸入電壓范圍均從負(fù)供電軌擴(kuò)展至正電源的1.3V范圍內(nèi)，非常適合3V或5V單電源應(yīng)用。\n\n MAX931–MAX934專門設(shè)計(jì)的輸出級(jí)可連續(xù)進(jìn)行高達(dá)40mA的拉電流操作。 ? 在擴(kuò)展溫度范圍內(nèi)具有超低靜態(tài)電流：4μA（最大值）(MAX931)\n\n? 電源：\n? +2.5V至+11V單電源\n\n? ±1.25V至±5.5V雙電源\n\n\n\n\n? 輸入電壓范圍包括負(fù)電源\n\n? 1.182V ±2%內(nèi)部帶隙基準(zhǔn)電壓源\n\n? 可調(diào)遲滯\n\n? TTL/CMOS兼容輸出\n\n? 12μs傳播延遲（10mV過驅(qū)）\n\n? 無開關(guān)瞬態(tài)開路電流\n\n? 40mA連續(xù)源電流\n\n? 節(jié)省空間的μMAX?封裝;

ADI

亞德諾

1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs

General Description The MAX9310A is a fast, low-skew 1:5 differential driver with selectable LVPECL inputs and LVDS outputs, designed for clock distribution applications. This device features an ultra-low propagation delay of 340ps with 48mA of supply current. Features ? Guaranteed 1.0GHz Opera

文件：176.33 Kbytes 頁數(shù)：11 Pages

MAXIM

美信

1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs

General Description The MAX9310A is a fast, low-skew 1:5 differential driver with selectable LVPECL inputs and LVDS outputs, designed for clock distribution applications. This device features an ultra-low propagation delay of 340ps with 48mA of supply current. Features ? Guaranteed 1.0GHz Opera

文件：176.33 Kbytes 頁數(shù)：11 Pages

MAXIM

美信

1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers designed for clock and data distribution. These devices allow selection between two inputs. The selected input is reproduced at 10 differential outputs. The differential inputs can be adapted to accept single-ended

文件：377.93 Kbytes 頁數(shù)：12 Pages

MAXIM

美信

1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers designed for clock and data distribution. These devices allow selection between two inputs. The selected input is reproduced at 10 differential outputs. The differential inputs can be adapted to accept single-ended

文件：377.93 Kbytes 頁數(shù)：12 Pages

MAXIM

美信

1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers designed for clock and data distribution. These devices allow selection between two inputs. The selected input is reproduced at 10 differential outputs. The differential inputs can be adapted to accept single-ended

文件：377.93 Kbytes 頁數(shù)：12 Pages

MAXIM

美信

1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers designed for clock and data distribution. These devices allow selection between two inputs. The selected input is reproduced at 10 differential outputs. The differential inputs can be adapted to accept single-ended

文件：377.93 Kbytes 頁數(shù)：12 Pages

MAXIM

美信

Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9312/MAX9314 are low skew, dual 1-to-5 differential drivers designed for clock and data distribution. These devices accept two inputs. Each input is reproduced at five differential outputs. The differential inputs can be adapted to accept single-ended inputs by connecti

文件：112.75 Kbytes 頁數(shù)：9 Pages

MAXIM

美信

Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9312/MAX9314 are low skew, dual 1-to-5 differential drivers designed for clock and data distribution. These devices accept two inputs. Each input is reproduced at five differential outputs. The differential inputs can be adapted to accept single-ended inputs by connecti

文件：112.75 Kbytes 頁數(shù)：9 Pages

MAXIM

美信