Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers

General Description The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output l

文件：187.44 Kbytes 頁(yè)數(shù)：15 Pages

MAXIM

美信

熱插拔、21位、直流平衡、LVDS解串器

MAX9234/MAX9236/MAX9238可將三路LVDS串行輸入解串為21路單端LVCMOS/LVTTL輸出。隨LVDS數(shù)據(jù)流接收到的并行LVDS時(shí)鐘提供解串定時(shí)。輸出具有獨(dú)立的供電引腳，允許1.8V至5V的輸出邏輯電平。這些器件均支持熱插拔，允許動(dòng)態(tài)頻率編程。\n MAX9234/MAX9236/MAX9238具有DC平衡特性，允許串行器和解串器之間通過(guò)AC耦合隔離。每個(gè)解串器對(duì)MAX9209/MAX9211/MAX9213/MAX9215串行器傳輸?shù)臄?shù)據(jù)進(jìn)行解碼。\n MAX9234具有上升沿輸出選通。MAX9236/MAX9238具有下降沿輸出選通。MAX9234/MAX9236/ \n? 動(dòng)態(tài)頻率編程 \n? 8MHz至34MHz (MAX9234/MAX9236) \n? 下降沿輸出選通(MAX9236/MAX9238) \n? /PWRDWN為低電平時(shí)輸出處于高阻，允許共用總線 \n? 無(wú)需外部元件的PLL \n? 獨(dú)立的輸出電源引腳提供1.8V、2.5V、3.3V和5V邏輯接口 \n? LVDS輸入符合ANSI TIA/EIA-644 LVDS標(biāo)準(zhǔn) \n? +3.3V主電源供電 \n? -40°C至+85°C工作溫度范圍;

ADI

亞德諾

Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers

General Description The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output l

文件：187.44 Kbytes 頁(yè)數(shù)：15 Pages

MAXIM

美信

Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers

文件：207.54 Kbytes 頁(yè)數(shù)：15 Pages

MAXIM

美信

Package：48-TFSOP（0.240"，6.10mm 寬）；包裝：托盤 功能：解串器 類別：集成電路（IC） 串行器，解串器 描述：IC DESERIALIZER 21BIT 48TSSOP

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亞德諾

Package：48-TFSOP（0.240"，6.10mm 寬）；包裝：卷帶（TR） 功能：解串器 類別：集成電路（IC） 串行器，解串器 描述：IC DESERIALIZER 21BIT 48TSSOP

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亞德諾