Ultra Low-Power, Single/Dual-Supply Comparators

General Description The MAX921–MAX924 single, dual, and quad micropower, low-voltage comparators feature the lowest power consumption available. These comparators draw less than 4μA supply current over temperature (MAX921/MAX922), and include an internal 1.182V ±1 voltage reference, programmable

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MAXIM

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Ultra Low-Power, Single/Dual-Supply Comparators

文件：192.13 Kbytes 頁數(shù)：17 Pages

MAXIM

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超低功耗、單/雙電源比較器

MAX921–MAX924單、雙和四路微功耗、低電壓比較器具有超低功耗。在整個工作溫度范圍內(nèi)，這些比較器僅消耗不足4μA電源電流(MAX921/MAX922)，并含有一個內(nèi)置的1.182V ±1%的基準(zhǔn)電壓源，具有可編程滯回，兼容于TTL/CMOS的輸出能夠吸收和源出電流。\n\n 此組比較器最適合用于3V或5V單電源系統(tǒng)中，也能夠工作于+2.5V至+11V單電源(或±1.25V至±5V雙電源)，每路比較器的輸入電壓擺幅從負(fù)電源到低于正電源電壓1.3V。\n\n MAX921–MAX924的獨特輸出級設(shè)計可以持續(xù)提供高達(dá)40mA的電流。由于消除了比較器改變邏輯狀態(tài)時 ? μMAX?及8引腳SO封裝(MAX921/MAX922/MAX923)\n? 超低靜態(tài)電流，全溫度范圍內(nèi)最大4μA (MAX921)\n? 供電電源：\n? +2.5V至+11V單電源\n? ±1.25V至±5.5V雙電源\n\n\n? 輸入電壓范圍包含了負(fù)電源電壓\n? 內(nèi)置1.182V ±1%帶隙基準(zhǔn)源\n? 可調(diào)滯回\n? TTL/CMOS兼容的輸出\n? 傳輸延遲時間12μs (10mV過驅(qū)動)\n? 無切換短路電流\n? 可持續(xù)提供40mA電流;

ADI

亞德諾

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

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MAXIM

美信

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

文件：904.71 Kbytes 頁數(shù)：18 Pages

MAXIM

美信

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

文件：904.71 Kbytes 頁數(shù)：18 Pages

MAXIM

美信

Programmable DC-Balanced 21-Bit Serializers

General Description The MAX9209/MAX9213 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization. The MAX9209/MAX9213 feature programmable DC balance, which allows isolation between the serializ

文件：477.18 Kbytes 頁數(shù)：20 Pages

MAXIM

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Programmable DC-Balanced 21-Bit Serializers

General Description The MAX9209/MAX9213 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization. The MAX9209/MAX9213 feature programmable DC balance, which allows isolation between the serializ

文件：477.18 Kbytes 頁數(shù)：20 Pages

MAXIM

美信

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

文件：904.71 Kbytes 頁數(shù)：18 Pages

MAXIM

美信

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

文件：904.71 Kbytes 頁數(shù)：18 Pages

MAXIM

美信