Delay Lines for High-Speed Clock Distribution Systems

General Description The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate

文件：159.71 Kbytes 頁數(shù)：6 Pages

MAXIM

美信

用于高速時鐘分配系統(tǒng)的延時線

MAX3620系列高性能無源延時線適用于QDR/QDRII同步存儲器系統(tǒng)。這些延時線支持高速收發(fā)器邏輯(HSTL)源端接，接收器無端接負載傳輸，可實現(xiàn)0.75ns、1.00ns、1.25ns和1.50ns的精確延時，產(chǎn)生四分之一時鐘相位。MAX3620提供小型3mm x 3mm封裝，含兩個等長，可差分驅(qū)動或單端驅(qū)動的延時線。 \n? 支持HSTL源端接傳輸線 \n? 全部無源設(shè)計 \n? 與100Ω差分和50Ω單端傳輸線兼容 \n? 小型3mm x 3mm封裝;

ADI

亞德諾

Delay Lines for High-Speed Clock Distribution Systems

General Description The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate

文件：159.71 Kbytes 頁數(shù)：6 Pages

MAXIM

美信

Delay Lines for High-Speed Clock Distribution Systems

General Description The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate

文件：159.71 Kbytes 頁數(shù)：6 Pages

MAXIM

美信

Delay Lines for High-Speed Clock Distribution Systems

General Description The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate

文件：159.71 Kbytes 頁數(shù)：6 Pages

MAXIM

美信

Delay Lines for High-Speed Clock Distribution Systems

General Description The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate

文件：159.71 Kbytes 頁數(shù)：6 Pages

MAXIM

美信

Package：6-WDFN 裸露焊盤；包裝：卷帶（TR） 功能：多重 類別：集成電路（IC） 延遲線 描述：IC DELAY LINE 1NS 6TDFN

AD

亞德諾

Package：6-WDFN 裸露焊盤；包裝：卷帶（TR） 功能：多重 類別：集成電路（IC） 延遲線 描述：IC DELAY LINE 1.25NS 6TDFN

AD

亞德諾