VCSO BASED CLOCK PLL WITH AUTOSWITCH

GENERALDESCRIPTION The M1040 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock protection, frequency translation and jitter attenuation in OC-12/48 class optical networking systems. It features dual differential inputs with two modes of input selection:

文件：436.58 Kbytes 頁(yè)數(shù)：12 Pages

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VCSO BASED CLOCK PLL WITH AUTOSWITCH

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VCSO BASED CLOCK PLL WITH AUTOSWITCH

GENERALDESCRIPTION The M1040 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock protection, frequency translation and jitter attenuation in OC-12/48 class optical networking systems. It features dual differential inputs with two modes of input selection:

文件：436.58 Kbytes 頁(yè)數(shù)：12 Pages

ICST

VCSO BASED CLOCK PLL WITH AUTOSWITCH

GENERALDESCRIPTION The M1040 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock protection, frequency translation and jitter attenuation in OC-12/48 class optical networking systems. It features dual differential inputs with two modes of input selection:

文件：436.58 Kbytes 頁(yè)數(shù)：12 Pages

ICST

VCSO BASED CLOCK PLL WITH AUTOSWITCH

GENERALDESCRIPTION The M1040 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock protection, frequency translation and jitter attenuation in OC-12/48 class optical networking systems. It features dual differential inputs with two modes of input selection:

文件：436.58 Kbytes 頁(yè)數(shù)：12 Pages

ICST

VCSO BASED CLOCK PLL WITH AUTOSWITCH

GENERALDESCRIPTION The M1040 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock protection, frequency translation and jitter attenuation in OC-12/48 class optical networking systems. It features dual differential inputs with two modes of input selection:

文件：436.58 Kbytes 頁(yè)數(shù)：12 Pages

ICST

VCSO BASEDCLOCKPLL WITHAUTOSWITCH

GENERALDESCRIPTION\nThe M1040 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock protection, frequency translation and jitter attenuation in OC-12/48 class optical networking systems. It features dual differential inputs with two modes of input selection: manu ◆Integrated SAW (surface acoustic wave) delay line; low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz)\n◆Output frequencies of 62.5 to 175 MHz; Two differen tial LVPECL outputs (CML, LVDS options available)\n◆Loss of Lock (LOL) indicator output\n◆Narrow Bandwidth control input (NBW pin); Init;

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