TWR-LS1021A Reference Manual

文件：964.93 Kbytes 頁數(shù)：71 Pages

FREESCALEFreescale Semiconductor, Inc

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LS1 32Bit ARM SoC, 600MHz, DDR3L, vTSEC, PCIe, USB2, CAN, 0 to 105C, Rev2.0

The QorIQ? LS1 family, which includes the LS1020A and LS1022A communications processors, is built on Layerscape architecture, the industry’s first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale.\nMembers of the value-performance tier, the QorIQ LS10 Core Complex? Dual Arm? v7 Cortex?-A7 32-bit cores, each supporting dual precision floating point and NEONSIMD module running up to 1.2 GHz (LS1020A) or 600 MHz (LS1022A)\n? 32 KB instruction and data L1 cache with single bit error detection and correction, ECC protection on both instruction and dat;

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LS1 32Bit ARM SoC, 600MHz, DDR3L, vTSEC, PCIe, USB2, CAN, SEC, -40 to 105C, Rev2.0

The QorIQ? LS1 family, which includes the LS1020A and LS1022A communications processors, is built on Layerscape architecture, the industry’s first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale.\nMembers of the value-performance tier, the QorIQ LS10 Core Complex? Dual Arm? v7 Cortex?-A7 32-bit cores, each supporting dual precision floating point and NEONSIMD module running up to 1.2 GHz (LS1020A) or 600 MHz (LS1022A)\n? 32 KB instruction and data L1 cache with single bit error detection and correction, ECC protection on both instruction and dat;

恩XP

LS1 32Bit ARM SoC, 600MHz, DDR3L, vTSEC, PCIe, USB2, CAN, -40 to 105C, Rev2.0

The QorIQ? LS1 family, which includes the LS1020A and LS1022A communications processors, is built on Layerscape architecture, the industry’s first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale.\nMembers of the value-performance tier, the QorIQ LS10 Core Complex? Dual Arm? v7 Cortex?-A7 32-bit cores, each supporting dual precision floating point and NEONSIMD module running up to 1.2 GHz (LS1020A) or 600 MHz (LS1022A)\n? 32 KB instruction and data L1 cache with single bit error detection and correction, ECC protection on both instruction and dat;

恩XP