絲?。?a target="_blank" title="Marking" href="/lmk04832w/em/marking.html">LMK04832W/EM；Package：CFP；LMK04832-SP Space Grade Ultra-Low-Noise JESD204B Dual-Loop Clock Jitter Cleaner

文件：2.82028 Mbytes 頁數(shù)：98 Pages

TI

德州儀器

LMK04832-SP Space Grade Ultra-Low-Noise JESD204B Dual-Loop Clock Jitter Cleaner

文件：2.35648 Mbytes 頁數(shù)：99 Pages

TI

德州儀器

LMK04832-SP Space Grade Ultra-Low-Noise JESD204B Dual-Loop Clock Jitter Cleaner

文件：2.35648 Mbytes 頁數(shù)：99 Pages

TI

德州儀器

絲印：LMK04832W/EM；Package：CFP；LMK04832-SP Space Grade Ultra-Low-Noise JESD204B Dual-Loop Clock Jitter Cleaner

文件：2.82028 Mbytes 頁數(shù)：98 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/lmk04832mpapsep/marking.html">LMK04832MPAPSEP；Package：HTQFP；LMK04832-SEP Space Grade Ultra-Low-Noise JESD204B/C Dual-Loop Clock Jitter Cleaner

1 Features ? VID#: V62/22612 – Total ionizing dose 30 krad (ELDRS-free) – SEL immune >43 MeV × cm2/mg – SEFI immune >43 MeV × cm2/mg ? Ambient temperature range: –55°C to 125°C ? Maximum clock output frequency: 3255 MHz ? Multi-mode: dual PLL, single PLL, and clock distribution ? 6-GHz ex

文件：3.05256 Mbytes 頁數(shù)：102 Pages

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德州儀器

耐輻射且符合 JESD204B/C 標(biāo)準(zhǔn)的 30krad 超低噪聲 3.2GHz、15 路輸出時鐘抖動清除器

The LMK04832-SEP is a high performance clock conditioner with JEDEC JESD204B/C support for space applications.\n\nThe 14 clock outputs from PLL2 can be configured to drive seven JESD204B/C converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC c ? VID#: V62/22612 \n? SEL immune >43 MeV × cm2/mg\n? Ambient temperature range: –55°C to 125°C\n? Multi-mode: dual PLL, single PLL, and clock distribution\n? Ultra-low noise, at 2500 MHz: \n? 64-fs RMS jitter (100 Hz to 20 MHz)\n? Ultra-low noise, at 3200 MHz: \n? 67-fs RMS jitter (100 Hz to 100 MHz;

TI

德州儀器

Space grade ultra low-Noise JESD204B compliant clock jitter cleaner

The LMK04832-SP is a high performance clock conditioner with JEDEC JESD204B support for space applications.\n\nThe 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupli ? SMD #5962R1723701VXC \n? SEL immune >120 MeV × cm2/mg\n? Maximum clock output frequency: 3255 MHz\n? 6-GHz external VCO or distribution input\n? 54-fs RMS jitter (12 kHz to 20 MHz)\n? –157.6-dBc/Hz noise floor\n? Ultra-low noise, at 3200 MHz: \n? 67-fs RMS jitter (100 Hz to 100 MHz)\n? PLL2 \n? PL;

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德州儀器

Package：64-WFQFN 裸露焊盤；包裝：卷帶（TR） 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：IC JITTER CLEANER 64WQFN

TI

德州儀器

Package：64-WFQFN 裸露焊盤；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：IC JITTER CLEANER 64WQFN

TI

德州儀器

Package：64-CFlatPack；包裝：托盤 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：SPACE GRADE ULTRA LOW-NOISE JESD

TI

德州儀器