| 型號(hào) | 下載 訂購(gòu) | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
絲印：LK5；Package：SOT-143；Transient Voltage Suppressors for ESD Protection Feature 450 and 588 Watts Peak Pulse Power per Line (tp=8/20μs) Protects two I/O lines Low clamping voltage Working voltages:5V and 12V Low leakage current IEC61000-4-2 (ESD) ±30kV (air), ±30kV (contact): IEC61000-4-4 (EFT) 40A (5/50ηs) Applications USB Power & Data Line Protection Et 文件：2.39004 Mbytes 頁(yè)數(shù)：4 Pages | UNSEMI 優(yōu)恩半導(dǎo)體 | UNSEMI | ||
絲?。?strong>LK5；Package：SOT-143；LOW CAPACITANCE TVS DIODE ARRAY 文件：548.98 Kbytes 頁(yè)數(shù)：7 Pages | LEIDITECH 雷卯電子 | LEIDITECH | ||
絲印：LK5C22212A；Package：VQFN；LMK5C22212A 2-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With JESD204B/C and BAW for Wireless Communications 1 Features ? Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz ? 2 high-performance Digital Phase Locked Loops (DPLLs) with 2 Analog Phase Locked Loops (APLLs 文件：4.59617 Mbytes 頁(yè)數(shù)：104 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/lk5c22212a-s1/marking.html">LK5C22212A-S1；Package：VQFN；LMK5C22212AS1 2-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With JESD204B/C and BAW for Wireless Communications With IEEE-1588 PTP Stack 1 Features ? Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz ? 2 high-performance Digital Phase Locked Loops (DPLLs) with 2 Analog Phase Locked Loops (APLLs 文件：4.47265 Mbytes 頁(yè)數(shù)：102 Pages | TI 德州儀器 | TI | ||
絲印：LK5C22212A；Package：VQFN；LMK5C22212A 2-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With JESD204B/C and BAW for Wireless Communications 1 Features ? Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz ? 2 high-performance Digital Phase Locked Loops (DPLLs) with 2 Analog Phase Locked Loops (APLLs 文件：4.59617 Mbytes 頁(yè)數(shù)：104 Pages | TI 德州儀器 | TI | ||
絲印：LK5C22212A-S1；Package：VQFN；LMK5C22212AS1 2-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With JESD204B/C and BAW for Wireless Communications With IEEE-1588 PTP Stack 1 Features ? Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz ? 2 high-performance Digital Phase Locked Loops (DPLLs) with 2 Analog Phase Locked Loops (APLLs 文件：4.47265 Mbytes 頁(yè)數(shù)：102 Pages | TI 德州儀器 | TI | ||
絲印：LK5C23208A；Package：VQFN；LMK5C23208A 2-DPLL 3-APLL 2-IN 8-OUT Network Synchronizer With JED204B/ JED204C and BAW VCO for Wireless Communications 1 Features ? Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz ? 2 high-performance Digital Phase Locked Loop (DPLL) with 3 Analog Phase Locked Loops (APLLs) 文件：4.86813 Mbytes 頁(yè)數(shù)：107 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/lk5c23208a/marking.html">LK5C23208A；Package：VQFN；LMK5C23208A 2-DPLL 3-APLL 2-IN 8-OUT Network Synchronizer With JED204B/ JED204C and BAW VCO for Wireless Communications 1 Features ? Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz ? 2 high-performance Digital Phase Locked Loop (DPLL) with 3 Analog Phase Locked Loops (APLLs) 文件：4.86813 Mbytes 頁(yè)數(shù)：107 Pages | TI 德州儀器 | TI | ||
絲印：LK5C33216A；Package：VQFN；LMK5C33216A Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications 1 Features ? Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz ? Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma 文件：4.6477 Mbytes 頁(yè)數(shù)：99 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/lk5c33216a-s1/marking.html">LK5C33216A-S1；Package：VQFN；LMK5C33216AS1 Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications 1 Features ? Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz ? Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma 文件：4.65279 Mbytes 頁(yè)數(shù)：99 Pages | TI 德州儀器 | TI |
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
SXSEMI |
23+ |
SOT143 |
900000 |
原廠授權(quán)一級(jí)代理,專業(yè)海外優(yōu)勢(shì)訂貨,價(jià)格優(yōu)勢(shì)、品種 |
詢價(jià) | ||
UN SEMICONDUCTOR |
24+ |
con |
10000 |
查現(xiàn)貨到京北通宇商城 |
詢價(jià) | ||
24+ |
N/A |
75000 |
一級(jí)代理-主營(yíng)優(yōu)勢(shì)-實(shí)惠價(jià)格-不悔選擇 |
詢價(jià) | |||
TINYSEMI |
23+ |
SOT-23 |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價(jià) | ||
SEMITEH |
25+ |
SOT23 |
30000 |
原裝正品,假一罰十! |
詢價(jià) | ||
TINYSEMI |
24+ |
SOT-23 |
60000 |
全新原裝現(xiàn)貨 |
詢價(jià) | ||
ZXWILL |
24+ |
SOT-23 |
98000 |
原裝現(xiàn)貨假一罰十 |
詢價(jià) | ||
SOCAY |
24+ |
SOT-23 |
9600 |
原裝現(xiàn)貨,優(yōu)勢(shì)供應(yīng),支持實(shí)單! |
詢價(jià) | ||
SOCAY |
2019+PB |
SOT23 |
2700 |
量有多以電話為準(zhǔn) |
詢價(jià) | ||
SOCAY |
新年份 |
SOT23 |
2700 |
原裝正品大量現(xiàn)貨,要多可發(fā)貨,實(shí)單帶接受價(jià)來(lái)談! |
詢價(jià) |
相關(guān)芯片絲印
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相關(guān)庫(kù)存
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