絲?。?strong>K4H；Package：DFN8；Low-power dual operational amplifier

Description This circuit consists of two independent, high gain operational amplifiers (op amps) that have frequency compensation implemented internally. They are designed specifically for automotive and industrial control systems. The circuit operates from a single power supply over a wide ra

文件：1.10942 Mbytes 頁數(shù)：28 Pages

STMICROELECTRONICS

意法半導(dǎo)體

絲?。?strong>K4H；Package：SOP；MOSFETs Silicon N-channel MOS

Applications ? Automotive ? Motor Drivers ? Switching Voltage Regulators Features (1) AEC-Q101 qualified (2) Small, thin package (3) Low drain-source on-resistance: RDS(ON) = 0.95 mΩ (typ.) (VGS = 10 V) (4) Low leakage current: IDSS = 10 μA (max) (VDS = 40 V) (5) Enhancement mode: Vth =

文件：597.43 Kbytes 頁數(shù)：10 Pages

TOSHIBA

東芝

128Mb DDR SDRAM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? Bidirectional data strobe(DQS) ? Four banks operation ? Differential clock inputs(CK and CK) ? DLL aligns DQ and DQS transition with CK transition ? MRS cycle with address key programs -. Read latency 2, 2.5 (

文件：669.27 Kbytes 頁數(shù)：53 Pages

SAMSUNG

三星

128Mb DDR SDRAM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? Bidirectional data strobe(DQS) ? Four banks operation ? Differential clock inputs(CK and CK) ? DLL aligns DQ and DQS transition with CK transition ? MRS cycle with address key programs -. Read latency 2, 2.5 (

文件：669.27 Kbytes 頁數(shù)：53 Pages

SAMSUNG

三星

128Mb DDR SDRAM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? Bidirectional data strobe(DQS) ? Four banks operation ? Differential clock inputs(CK and CK) ? DLL aligns DQ and DQS transition with CK transition ? MRS cycle with address key programs -. Read latency 2, 2.5 (

文件：669.27 Kbytes 頁數(shù)：53 Pages

SAMSUNG

三星

128Mb DDR SDRAM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? Bidirectional data strobe(DQS) ? Four banks operation ? Differential clock inputs(CK and CK) ? DLL aligns DQ and DQS transition with CK transition ? MRS cycle with address key programs -. Read latency 2, 2.5 (

文件：669.27 Kbytes 頁數(shù)：53 Pages

SAMSUNG

三星

128Mb DDR SDRAM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? Bidirectional data strobe(DQS) ? Four banks operation ? Differential clock inputs(CK and CK) ? DLL aligns DQ and DQS transition with CK transition ? MRS cycle with address key programs -. Read latency 2, 2.5 (

文件：669.27 Kbytes 頁數(shù)：53 Pages

SAMSUNG

三星

128Mb DDR SDRAM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? Bidirectional data strobe(DQS) ? Four banks operation ? Differential clock inputs(CK and CK) ? DLL aligns DQ and DQS transition with CK transition ? MRS cycle with address key programs -. Read latency 2, 2.5 (

文件：669.27 Kbytes 頁數(shù)：53 Pages

SAMSUNG

三星

128Mb DDR SDRAM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? Bidirectional data strobe(DQS) ? Four banks operation ? Differential clock inputs(CK and CK) ? DLL aligns DQ and DQS transition with CK transition ? MRS cycle with address key programs -. Read latency 2, 2.5 (

文件：669.27 Kbytes 頁數(shù)：53 Pages

SAMSUNG

三星

128Mb DDR SDRAM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? Bidirectional data strobe(DQS) ? Four banks operation ? Differential clock inputs(CK and CK) ? DLL aligns DQ and DQS transition with CK transition ? MRS cycle with address key programs -. Read latency 2, 2.5 (

文件：669.27 Kbytes 頁數(shù)：53 Pages

SAMSUNG

三星