IS43DR16640B-25DBL集成電路（IC）的存儲器規(guī)格書PDF中文資料

FEATURES

? Clock frequency up to 400MHz

? 8 internal banks for concurrent operation

? 4‐bit prefetch architecture

? Programmable CAS Latency: 3, 4, 5, 6 and 7

? Programmable Additive Latency: 0, 1, 2, 3, 4, 5

and 6

? Write Latency = Read Latency‐1

? Programmable Burst Sequence: Sequential or

Interleave

? Programmable Burst Length: 4 and 8

? Automatic and Controlled Precharge Command

? Power Down Mode

? Auto Refresh and Self Refresh

? Refresh Interval: 7.8 ?s (8192 cycles/64 ms)

? ODT (On‐Die Termination)

? Weak Strength Data‐Output Driver Option

? Bidirectional differential Data Strobe (Singleended

data‐strobe is an optional feature)

? On‐Chip DLL aligns DQ and DQs transitions with

CK transitions

? DQS# can be disabled for single‐ended data

strobe

? Read Data Strobe supported (x8 only)

? Differential clock inputs CK and CK#

? VDD and VDDQ = 1.8V ± 0.1V

? PASR (Partial Array Self Refresh)

? SSTL_18 interface

? tRAS lockout supported

? Operating temperature:

Commercial (TA = 0°C to 70°C ; TC = 0°C to 85°C)

Industrial (TA = ‐40°C to 85°C; TC = ‐40°C to 95°C)

Automotive, A1 (TA = ‐40°C to 85°C; TC = ‐40°C to 95°C)

Automotive, A2 (TA = ‐40°C to 105°C; TC = ‐40°C to

105°C)