Low Cost DDR Phase Lock Loop Zero Delay Buffer

Output Features DDR Zero Delay Clock Buffer ? Low skew, low jitter PLL clock driver ? I2C for functional and output control ? Feedback pins for input to output synchronization ? Spread Spectrum tolerant inputs ? 3.3V tolerant CLK_INT input

文件：160.26 Kbytes 頁數(shù)：9 Pages

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DDR Phase Lock Loop Zero Delay Clock Buffer

Product Description/Features: ? Low skew, low jitter PLL clock driver ? Max frequency supported = 266MHz (DDR 533) ? I2C for functional and output control ? Feedback pins for input to output synchronization ? Spread Spectrum tolerant inputs ? 3.3V tolerant CLK_INT input Recommended Applicat

文件：126.1 Kbytes 頁數(shù)：7 Pages

ICST

DDR Phase Lock Loop Zero Delay Clock Buffer

Renesas

瑞薩

DDR Phase Lock Loop Zero Delay Clock Buffer

Product Description/Features: ? Low skew, low jitter PLL clock driver ? Max frequency supported = 266MHz (DDR 533) ? I2C for functional and output control ? Feedback pins for input to output synchronization ? Spread Spectrum tolerant inputs ? 3.3V tolerant CLK_INT input Recommended Applicat

文件：126.1 Kbytes 頁數(shù)：7 Pages

ICST

Low Cost DDR Phase Lock Loop Zero Delay Buffer

Output Features DDR Zero Delay Clock Buffer ? Low skew, low jitter PLL clock driver ? I2C for functional and output control ? Feedback pins for input to output synchronization ? Spread Spectrum tolerant inputs ? 3.3V tolerant CLK_INT input

文件：160.26 Kbytes 頁數(shù)：9 Pages

RENESAS

瑞薩