LOW SKEW, 1-TO-5, DIFFERENTIAL-TOHSTL FANOUT BUFFER

? Five differential HSTL compatible outputs ? Selectable differential CLK0, CLK0 or LVCMOS/LVTTL clock inputs ? CLK0, CLK0 pair can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL, SSTL ? CLK1 can accept the following input levels: LVCMOS or LVTTL ? Output frequency

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LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

GENERAL DESCRIPTION The ICS85214 is a low skew, high performance 1-to-5 Differential-to-HSTL Fanout Buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from ICS. The CLK0, nCLK0 pair can accept most standard differential input levels. The single ended CLK1 input a

文件：119.69 Kbytes 頁數(shù)：16 Pages

ICST

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

GENERAL DESCRIPTION\nThe ICS85214 is a low skew, high performance 1-to-5 Differential-to-HSTL Fanout Buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from ICS. The CLK0, nCLK0 pair can accept most standard differential input levels. The single ended CLK1 input accep ? 5 differential HSTL compatible outputs\n? Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL clock inputs\n? CLK0, nCLK0 pair can accept the following differential input levels: LVDS, LVPECL, HSTL, SSTL, HCSL\n? CLK1 can accept the following input levels: LVCMOS or LVTTL\n? Output frequency up to;

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LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

GENERAL DESCRIPTION The ICS85214 is a low skew, high performance 1-to-5 Differential-to-HSTL Fanout Buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from ICS. The CLK0, nCLK0 pair can accept most standard differential input levels. The single ended CLK1 input a

文件：119.69 Kbytes 頁數(shù)：16 Pages

ICST

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

GENERAL DESCRIPTION The ICS85214I is a low skew, high performance 1-to-5 Differential-to-HSTL Fanout Buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from ICS. The CLK0, nCLK0 pair can accept most standard differential input levels. The single ended CLK1 input

文件：189 Kbytes 頁數(shù)：15 Pages

ICST

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

GENERAL DESCRIPTION The ICS85214I is a low skew, high performance 1-to-5 Differential-to-HSTL Fanout Buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from ICS. The CLK0, nCLK0 pair can accept most standard differential input levels. The single ended CLK1 input

文件：189 Kbytes 頁數(shù)：15 Pages

ICST

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

GENERAL DESCRIPTION The ICS85214I is a low skew, high performance 1-to-5 Differential-to-HSTL Fanout Buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from ICS. The CLK0, nCLK0 pair can accept most standard differential input levels. The single ended CLK1 input

文件：189 Kbytes 頁數(shù)：15 Pages

ICST

Low Skew, 1-to-5, Differential-to-HSTL Fanout Buffer

FEATURES ? Five differential HSTL compatible outputs ? Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL clock inputs ? CLK0, nCLK0 pair can accept the following differential input levels: LVDS, LVPECL, HSTL, HCSL ? CLK1 can accept the following input levels: LVCMOS or LVTTL ? Output

文件：391.77 Kbytes 頁數(shù)：17 Pages

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瑞薩

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

GENERAL DESCRIPTION The ICS85214I is a low skew, high performance 1-to-5 Differential-to-HSTL Fanout Buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from ICS. The CLK0, nCLK0 pair can accept most standard differential input levels. The single ended CLK1 input

文件：189 Kbytes 頁數(shù)：15 Pages

ICST

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

GENERAL DESCRIPTION\nThe ICS85214I is a low skew, high performance 1-to-5 Differential-to-HSTL Fanout Buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from ICS. The CLK0, nCLK0 pair can accept most standard differential input levels. The single ended CLK1 input acce ? 5 differential HSTL compatible outputs\n? Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL clock inputs\n? CLK0, nCLK0 pair can accept the following differential input levels: LVDS, LVPECL, HSTL, SSTL, HCSL\n? CLK1 can accept the following input levels: LVCMOS or LVTTL\n? Output frequency up to;

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