Clock Generator for Cavium Processors

Features ? One selectable clock for DDR 400/533/667, LVPECL/LVDS interface levels ? Nine LVCMOS/ LVTTL outputs, 15Ω typical output impedance ? Selectable external crystal or differential input source ? Crystal oscillator interface designed for 25MHz, parallel resonant crystal ? Differential

文件：1.79228 Mbytes 頁數(shù)：30 Pages

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Clock Generator for Cavium Processors

General Description The 8430S10I-03 is a PLL-based clock generator specifically designed for Cavium Networks SoC processors. This high performance device is optimized to generate the processor core reference clock, the DDR reference clocks, the PCI/PCI-X bus clocks, and the clocks for both th

文件：830.35 Kbytes 頁數(shù)：32 Pages

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Clock Generator for Cavium Processors

文件：1.08423 Mbytes 頁數(shù)：31 Pages

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Clock Generator for Cavium Processors

Features ? One selectable clock for DDR 400/533/667, LVPECL/LVDS interface levels ? Nine LVCMOS/ LVTTL outputs, 15Ω typical output impedance ? Selectable external crystal or differential input source ? Crystal oscillator interface designed for 25MHz, parallel resonant crystal ? Differential

文件：1.79228 Mbytes 頁數(shù)：30 Pages

RENESAS

瑞薩

Clock Generator for Cavium Processors

Features ? One selectable clock for DDR 400/533/667, LVPECL/LVDS interface levels ? Nine LVCMOS/ LVTTL outputs, 15Ω typical output impedance ? Selectable external crystal or differential input source ? Crystal oscillator interface designed for 25MHz, parallel resonant crystal ? Differential

文件：1.79228 Mbytes 頁數(shù)：30 Pages

RENESAS

瑞薩