LOW PHASE NOISE CLOCK MULTIPLIER

Features ? Fully integrated PLL, no external loop filter required ? Differential 3.3 V LVPECL outputs ? Uses fundamental crystal or clock — Crystal input frequency: 10 to 27MHz — Clock input: 10 to 38MHz (mulitply by 6) 10 to 31MHz (all other multiply settings) ? Output clocks up to 230 MHz

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LOW PHASE NOISE CLOCK MULTIPLIER

Description The ICS601-21 is a low-cost, low phase noise, high performance clock synthesizer for applications which require low phase noise and low jitter. It is ICS’ lowest phase noise multiplier. Using ICS’ patented analog and digital Phase Locked Loop (PLL) techniques, the chip accepts a 10 -

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ICST

SOP16

IDT

上傳：深圳市旺財(cái)半導(dǎo)體有限公司

TSSOP8

INTEGRA

上傳：深圳市旺財(cái)半導(dǎo)體有限公司

SOP8

IDT

上傳：深圳市拓億芯電子有限公司