8-bit bidirectional universal shift register

DESCRIPTION The 74F166 is a high speed 8–bit shift register that has fully synchronous serial parallel data entry selected by an active low parallel enable (PE) input. When the PE is low one setup time before the low–to–high clock transition, parallel data is entered into the register. FEA

文件：94.75 Kbytes 頁數(shù)：12 Pages

PHI

PHI

8-bit bidirectional universal shift register

DESCRIPTION\nThe 74F166 is a high speed 8–bit shift register that has fully synchronous serial parallel data entry selected by an active low parallel enable (PE) input. When the PE is low one setup time before the low–to–high clock transition, parallel data is entered into the register.FEATURES\n? H ? High impedance NPN base inputs for reduced loading (20μA in high and low states)\n? Synchronous parallel to serial applications\n? Synchronous serial data input for easy expansion\n? Clock enable for ”do nothing” mode\n? Asynchronous master reset\n? Expandable to 16 bits in 8–bit increments\n? Ind;

恩XP

8-bit bidirectional universal shift register

DESCRIPTION The 74F166 is a high speed 8–bit shift register that has fully synchronous serial parallel data entry selected by an active low parallel enable (PE) input. When the PE is low one setup time before the low–to–high clock transition, parallel data is entered into the register. FEA

文件：94.75 Kbytes 頁數(shù)：12 Pages

PHI

PHI

8-bit bidirectional universal shift register

DESCRIPTION The 74F166 is a high speed 8–bit shift register that has fully synchronous serial parallel data entry selected by an active low parallel enable (PE) input. When the PE is low one setup time before the low–to–high clock transition, parallel data is entered into the register. FEA

文件：94.75 Kbytes 頁數(shù)：12 Pages

PHI

PHI