High Current Toroidal Inductors

文件：1.15675 Mbytes 頁數(shù)：3 Pages

BITECH

High Current Toroidal Inductors

文件：779.69 Kbytes 頁數(shù)：3 Pages

TTELEC

NPN EPITAXIAL PLANAR TRANSISTOR

Description The HM5401 is designed for general purpose applications requiring high breakdown voltages. Features ? High current-emitter breakdown voltage.VCEO=150V(@IC=1mA) ? Complements to NPN type HM5551

文件：34.89 Kbytes 頁數(shù)：4 Pages

HSMC

華昕

256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword ? 16-bit ? 4-bank/8-Mword ? 8-bit ? 4-bank/ 16-Mword ? 4-bit ? 4-bank

Description The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS)

文件：489.7 Kbytes 頁數(shù)：65 Pages

ELPIDA

爾必達(dá)

256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword ? 16-bit ? 4-bank/8-Mword ? 8-bit ? 4-bank/ 16-Mword ? 4-bit ? 4-bank

Description The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS)

文件：489.7 Kbytes 頁數(shù)：65 Pages

ELPIDA

爾必達(dá)

256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword ? 16-bit ? 4-bank/8-Mword ? 8-bit ? 4-bank/ 16-Mword ? 4-bit ? 4-bank

Description The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS)

文件：489.7 Kbytes 頁數(shù)：65 Pages

ELPIDA

爾必達(dá)

256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword ? 16-bit ? 4-bank/8-Mword ? 8-bit ? 4-bank/ 16-Mword ? 4-bit ? 4-bank

Description The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS)

文件：489.7 Kbytes 頁數(shù)：65 Pages

ELPIDA

爾必達(dá)

256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword ? 16-bit ? 4-bank/8-Mword ? 8-bit ? 4-bank/ 16-Mword ? 4-bit ? 4-bank

Description The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS)

文件：489.7 Kbytes 頁數(shù)：65 Pages

ELPIDA

爾必達(dá)

256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword ? 16-bit ? 4-bank/8-Mword ? 8-bit ? 4-bank/ 16-Mword ? 4-bit ? 4-bank

Description The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS)

文件：489.7 Kbytes 頁數(shù)：65 Pages

ELPIDA

爾必達(dá)

256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword ? 16-bit ? 4-bank/8-Mword ? 8-bit ? 4-bank/ 16-Mword ? 4-bit ? 4-bank

Description The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS)

文件：489.7 Kbytes 頁數(shù)：65 Pages

ELPIDA

爾必達(dá)