512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword ? 16-bit ? 4-bank/16-Mword ? 8-bit ? 4-bank /32-Mword ? 4-bit ? 4-bank PC/133, PC/100 SDRAM

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512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword ? 16-bit ? 4-bank/16-Mword ? 8-bit ? 4-bank /32-Mword ? 4-bit ? 4-bank PC/133, PC/100 SDRAM

文件：368.67 Kbytes 頁數(shù)：63 Pages

ELPIDA

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512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword ? 16-bit ? 4-bank/16-Mword ? 8-bit ? 4-bank /32-Mword ? 4-bit ? 4-bank PC/133, PC/100 SDRAM

文件：368.67 Kbytes 頁數(shù)：63 Pages

ELPIDA

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512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword ? 16-bit ? 4-bank/16-Mword ? 8-bit ? 4-bank /32-Mword ? 4-bit ? 4-bank PC/133, PC/100 SDRAM

文件：368.67 Kbytes 頁數(shù)：63 Pages

ELPIDA

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512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword ? 16-bit ? 4-bank/16-Mword ? 8-bit ? 4-bank /32-Mword ? 4-bit ? 4-bank PC/133, PC/100 SDRAM

文件：368.67 Kbytes 頁數(shù)：63 Pages

ELPIDA

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512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword ?16-bit ?4-bank/16-Mword ?8-bit ?4-bank /32-Mword ?4-bit ?4-bank PC/133, PC/100 SDRAM

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512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM

Description\nThe HM5259165B is a 512-Mbit SDRAM organized as 8388608-word × 16-bit × 4 bank. The HM5259805B is a 512-Mbit SDRAM organized as 16777216-word × 8-bit × 4 bank. The HM5259405B is a 512-Mbit SDRAM organized as 33554432-word × 4-bit × 4 bank. All inputs and outputs are referred to the risi ? 3.3 V power supply\n? Clock frequency: 133 MHz/100 MHz (max)\n? LVTTL interface\n? Single pulsed RAS\n? 4 banks can operate simultaneously and independently\n? Burst read/write operation and burst read/single write operation capability\n? Programmable burst length: 1/2/4/8\n? 2 variations of burst;

Micron

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