Programmable 4-bit binary down counter

DESCRIPTION The HEF4526B is a synchronous programmable 4-bit binary down counter with an active HIGH and an active LOW clock input (CP0, CP1), an asynchronous parallel load input (PL), four parallel inputs (P0 to P3), a cascade feedback input (CF), four buffered parallel outputs (O0 to O3), a ter

文件：109.2 Kbytes 頁數(shù)：10 Pages

PHI

PHI

Programmable 4-bit binary down counter

DESCRIPTION The HEF4526B is a synchronous programmable 4-bit binary down counter with an active HIGH and an active LOW clock input (CP0, CP1), an asynchronous parallel load input (PL), four parallel inputs (P0 to P3), a cascade feedback input (CF), four buffered parallel outputs (O0 to O3), a ter

文件：109.2 Kbytes 頁數(shù)：10 Pages

PHI

PHI

Programmable 4-bit binary down counter

DESCRIPTION The HEF4526B is a synchronous programmable 4-bit binary down counter with an active HIGH and an active LOW clock input (CP0, CP1), an asynchronous parallel load input (PL), four parallel inputs (P0 to P3), a cascade feedback input (CF), four buffered parallel outputs (O0 to O3), a ter

文件：109.2 Kbytes 頁數(shù)：10 Pages

PHI

PHI

Programmable 4-bit binary down counter

DESCRIPTION The HEF4526B is a synchronous programmable 4-bit binary down counter with an active HIGH and an active LOW clock input (CP0, CP1), an asynchronous parallel load input (PL), four parallel inputs (P0 to P3), a cascade feedback input (CF), four buffered parallel outputs (O0 to O3), a ter

文件：109.2 Kbytes 頁數(shù)：10 Pages

PHI

PHI