Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

文件：75.76 Kbytes 頁(yè)數(shù)：8 Pages

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Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

文件：75.76 Kbytes 頁(yè)數(shù)：8 Pages

PHI

PHI

Dual 64-bit static shift register

General description The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (nCP), data input (nD), parallel input-enable/output-enable (nPE/OE) and four 3-state outputs of the 16th, 32nd, 48th, and 64th bit positions (nQ16 to nQ64). Dat

文件：152.05 Kbytes 頁(yè)數(shù)：15 Pages

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Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

文件：75.76 Kbytes 頁(yè)數(shù)：8 Pages

PHI

PHI

Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

文件：75.76 Kbytes 頁(yè)數(shù)：8 Pages

PHI

PHI

Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

文件：75.76 Kbytes 頁(yè)數(shù)：8 Pages

PHI

PHI

Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

文件：75.76 Kbytes 頁(yè)數(shù)：8 Pages

PHI

PHI

Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

文件：75.76 Kbytes 頁(yè)數(shù)：8 Pages

PHI

PHI

Dual 64-bit static shift register

General description The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (nCP), data input (nD), parallel input-enable/output-enable (nPE/OE) and four 3-state outputs of the 16th, 32nd, 48th, and 64th bit positions (nQ16 to nQ64). Dat

文件：152.05 Kbytes 頁(yè)數(shù)：15 Pages

恩XP

Dual 64-bit static shift register

General description\nThe HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (nCP), data input (nD), parallel input-enable/output-enable (nPE/OE) and four 3-state outputs of the 16th, 32nd, 48th, and 64th bit positions (nQ16 to nQ64). Data ■ Tolerant of slow clock rise and fall times\n■ Fully static operation\n■ 5 V, 10 V, and 15 V parametric ratings\n■ Standardized symmetrical output characteristics\n■ Operates across the full industrial temperature range ?40 °C to +85 °C\n■ Complies with JEDEC standard JESD 13-BApplications\n■ Indus;

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