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                >HEF4094BT>規(guī)格書列表
                
    
            
    
                
    
                    
    型號下載 訂購功能描述制造商 上傳企業(yè)LOGO
    
                    
    HEF4094BT
    8-stage shift-and-store bus register
    
DESCRIPTION
The HEF4094B is an 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs O0 to O7. The parallel outputs may be connected directly to common bus lines.
    文件：81.02 Kbytes 頁數(shù)：7 Pages
    PHI
    PHI
    PHI
    

    HEF4094BT
    8-stage shift-and-store bus register
    
General description
The HEF4094B is an 8-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is shifted on p
    文件：103.36 Kbytes 頁數(shù)：17 Pages
    恩XP
    恩XP
    

    HEF4094BT
    8-stage shift-and-store register
    
1. General description
The HEF4094B is an 8-bit serial-in/serial or parallel-out shift register with a storage register and
3-state outputs. Both the shift and storage register have separate clocks. The device features a
serial input (D) and two serial outputs (QS1 and QS2) to enable cascading.
    文件：263.2 Kbytes 頁數(shù)：15 Pages
    NEXPERIA
    安世
    

    HEF4094BT
    8-stage shift-and-store register Rev. 11 ??29 August 2013
    文件：204.26 Kbytes 頁數(shù)：20 Pages
    恩XP
    恩XP
    

    HEF4094BT
    8-stage shift-and-store register
    文件：169.66 Kbytes 頁數(shù)：19 Pages
    恩XP
    恩XP
    

    HEF4094BT
    8-stage shift-and-store register
    文件：204.26 Kbytes 頁數(shù)：20 Pages
    PHI
    PHI
    PHI
    

    HEF4094BT-Q100
    8-stage shift-and-store register
    
1. General description
The HEF4094B-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register
and 3-state outputs. Both the shift and storage register have separate clocks. The device features
a serial input (D) and two serial outputs (QS1 and QS2) to enable casca
    文件：263.04 Kbytes 頁數(shù)：15 Pages
    NEXPERIA
    安世
    

    HEF4094BTS
    8-stage shift-and-store bus register
    
General description
The HEF4094B is an 8-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is shifted on p
    文件：103.36 Kbytes 頁數(shù)：17 Pages
    恩XP
    恩XP
    

    HEF4094BTT
    8-stage shift-and-store register
    
1. General description
The HEF4094B is an 8-bit serial-in/serial or parallel-out shift register with a storage register and
3-state outputs. Both the shift and storage register have separate clocks. The device features a
serial input (D) and two serial outputs (QS1 and QS2) to enable cascading.
    文件：263.2 Kbytes 頁數(shù)：15 Pages
    NEXPERIA
    安世
    

    HEF4094BTT-Q100
    8-stage shift-and-store register
    
1. General description
The HEF4094B-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register
and 3-state outputs. Both the shift and storage register have separate clocks. The device features
a serial input (D) and two serial outputs (QS1 and QS2) to enable casca
    文件：263.04 Kbytes 頁數(shù)：15 Pages
    NEXPERIA
    安世
    

    
            
    
		
        
    
            
    
                
    技術(shù)參數(shù)
    
            
    
            
      
            	
    • VCC (V)：
      3.0?-?15
    • Logic switching levels：
      CMOS
    • Output drive capability (mA)：
      ± 2.4
    • tpd (ns)：
      50
    • fmax (MHz)：
      28
    • Nr of bits：
      8
    • Power dissipation considerations：
      medium
    • Tamb (°C)：
      -40~85
    • Rth(j-a) (K/W)：
      89
    • Ψth(j-top) (K/W)：
      8.1
    • Rth(j-c) (K/W)：
      48
    • Package name：
      SO16
    
            
    
        
    
            
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