Quadruple D-type register with 3-state outputs

DESCRIPTION The HEF4076B is a quadruple edge-triggered D-type flip-flop with four data inputs (D0to D3), two active LOW data enable inputs (ED0andED1), a common clock input (CP), four 3-state outputs (O0to O3), two active LOW output enable inputs (EO0andEO1), and an overriding asynchronous mast

文件：70.34 Kbytes 頁數(shù)：7 Pages

PHI

PHI

Quadruple D-type register with 3-state outputs

DESCRIPTION The HEF4076B is a quadruple edge-triggered D-type flip-flop with four data inputs (D0to D3), two active LOW data enable inputs (ED0andED1), a common clock input (CP), four 3-state outputs (O0to O3), two active LOW output enable inputs (EO0andEO1), and an overriding asynchronous mast

文件：70.34 Kbytes 頁數(shù)：7 Pages

PHI

PHI

Quadruple D-type register with 3-state outputs

DESCRIPTION The HEF4076B is a quadruple edge-triggered D-type flip-flop with four data inputs (D0to D3), two active LOW data enable inputs (ED0andED1), a common clock input (CP), four 3-state outputs (O0to O3), two active LOW output enable inputs (EO0andEO1), and an overriding asynchronous mast

文件：70.34 Kbytes 頁數(shù)：7 Pages

PHI

PHI

Quadruple D-type register with 3-state outputs

DESCRIPTION The HEF4076B is a quadruple edge-triggered D-type flip-flop with four data inputs (D0to D3), two active LOW data enable inputs (ED0andED1), a common clock input (CP), four 3-state outputs (O0to O3), two active LOW output enable inputs (EO0andEO1), and an overriding asynchronous mast

文件：70.34 Kbytes 頁數(shù)：7 Pages

PHI

PHI