4-bit synchronous decade counter with asynchronous reset

DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count ena

文件：155.57 Kbytes 頁數(shù)：10 Pages

PHI

PHI

4-bit synchronous decade counter with asynchronous reset

DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count ena

文件：155.57 Kbytes 頁數(shù)：10 Pages

PHI

PHI

4-bit synchronous decade counter with asynchronous reset

DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count ena

文件：155.57 Kbytes 頁數(shù)：10 Pages

PHI

PHI

4-bit synchronous decade counter with asynchronous reset

DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count ena

文件：155.57 Kbytes 頁數(shù)：10 Pages

PHI

PHI