Dual 4-bit static shift register

DESCRIPTION The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information pr

文件：58.08 Kbytes 頁數(shù)：5 Pages

PHI

PHI

Dual 4-bit static shift register

DESCRIPTION The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information pr

文件：58.08 Kbytes 頁數(shù)：5 Pages

PHI

PHI

Dual 4-bit static shift register

DESCRIPTION The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information pr

文件：58.08 Kbytes 頁數(shù)：5 Pages

PHI

PHI

EPDM Snap-In Liquid Tight Bushings

文件：95.85 Kbytes 頁數(shù)：1 Pages

HEYCO

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

Description CD4015BMS consists of two identical, independent, 4-stage serial-input/parallel output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. “Q” outputs are available from each of the four stages on both registers. All register stages

文件：118.72 Kbytes 頁數(shù)：8 Pages

INTERSIL

EPDM Snap-In Liquid Tight Bushings

文件：95.85 Kbytes 頁數(shù)：1 Pages

HEYCO