Dual D-type Flip-Flops (with Preset and Clear)

Description The flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at thte data input is transferred to the output during the positive going transition to the clock pulse. Preset and clear are independent of the clock and accomplished by

文件：58.03 Kbytes 頁數(shù)：9 Pages

HITACHIHitachi Semiconductor

日立日立公司

Dual D-type Flip-Flops (with Preset and Clear)

Description The flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive going transition to the clock pulse. Preset and clear are independent of the clock and accomplished by a

文件：108.32 Kbytes 頁數(shù)：8 Pages

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Dual D-type Flip-Flops (with Preset and Clear)

Description\nThe flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at thte data input is transferred to the output during the positive going transition to the clock pulse.\nPreset and clear are independent of the clock and accomplished by a ? High Speed Operation: tpd (Clock to Q or Q) = 14 ns typ (CL = 50 pF)\n? High Output Current: Fanout of 10 LSTTL Loads\n? Wide Operating Voltage: VCC = 2 to 6 V\n? Low Input Current: 1 μA max\n? Low Quiescent Supply Current: ICC (static) = 2 μA max (Ta = 25°C);

HITACHI

日立

Dual D-type Flip-Flops (with Preset and Clear)

Description\nThe flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive going transition to the clock pulse. Preset and clear are independent of the clock and accomplished by a lo ? High Speed Operation: tpd (Clock to Q or Q) = 14 ns typ (CL = 50 pF)\n? High Output Current: Fanout of 10 LSTTL Loads\n? Wide Operating Voltage: VCC = 2 to 6 V\n? Low Input Current: 1 μA max\n? Low Quiescent Supply Current: ICC (static) = 2 μA max (Ta = 25°C);

Renesas

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Dual D-type Flip-Flops (with Preset and Clear)

Description The flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at thte data input is transferred to the output during the positive going transition to the clock pulse. Preset and clear are independent of the clock and accomplished by

文件：58.03 Kbytes 頁數(shù)：9 Pages

HITACHIHitachi Semiconductor

日立日立公司

Dual D-type Flip-Flops (with Preset and Clear)

Description The flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive going transition to the clock pulse. Preset and clear are independent of the clock and accomplished by a

文件：108.32 Kbytes 頁數(shù)：8 Pages

RENESAS

瑞薩

Dual D-type Flip-Flops (with Preset and Clear)

Description The flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive going transition to the clock pulse. Preset and clear are independent of the clock and accomplished by a

文件：108.32 Kbytes 頁數(shù)：8 Pages

RENESAS

瑞薩

Dual D-type Flip-Flops (with Preset and Clear)

Description The flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive going transition to the clock pulse. Preset and clear are independent of the clock and accomplished by a

文件：108.32 Kbytes 頁數(shù)：8 Pages

RENESAS

瑞薩

Dual D-type Flip-Flops (with Preset and Clear)

文件：169.7 Kbytes 頁數(shù)：10 Pages

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瑞薩

Dual D-type Flip-Flops (with Preset and Clear)

文件：169.7 Kbytes 頁數(shù)：10 Pages

RENESAS

瑞薩