Radiation Hardened Synchronous Counter

Description The Intersil HCS161MS is a Radiation Hardened 4-Input Binary; synchronous counter featuring asynchronous reset and lookahead carry logic. The HCS161 has an active-low master reset to zero, MR. A low level at the synchronous parallel enable, SPE, disables counting and allows data at th

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INTERSIL

Radiation Hardened Synchronous Counter

Features ? 3 Micron Radiation Hardened SOS CMOS ? Total Dose 200K RAD (Si) ? SEP Effective LET No Upsets: >100 MEV-cm2/mg ? Single Event Upset (SEU) Immunity 1 x 1012 RAD (Si)/s ? Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse ? Cos

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CMOS Synchronous Counter

The Intersil HCS161MS is a Radiation Hardened 4-Input Binary; synchronous counter featuring asynchronous reset and lookahead carry logic. The HCS161 has an active-low master reset to zero, MR. A low level at the synchronous parallel enable, SPE, disables counting and allows data at the preset inputs ? 3 Micron Radiation Hardened SOS CMOS \n? Total Dose 200K RAD (Si) \n? SEP Effective LET No Upsets: >100 MEV-cm2/mg \n? Single Event Upset (SEU) Immunity -9 Errors/Bit-Day (Typ) \n? Dose Rate Survivability: >1 x 1012 RAD (Si)/s \n? Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse \n? Cosmic Ray Upset Im;

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瑞薩

Radiation Hardened Synchronous Counter

Description The Intersil HCTS161AMS high-reliability high-speed presettable four-bit binary synchronous counter features asynchronous reset and look-ahead carry logic. The HCTS161AMS has an active-low master reset to zero, MR. A low level at the synchronous parallel enable, SPE, disables counting

文件：115.77 Kbytes 頁(yè)數(shù)：9 Pages

INTERSIL

Radiation Hardened Synchronous Counter

Features ? 3 Micron Radiation Hardened CMOS SOS ? Total Dose 200K RAD (Si) ? Minimum LET for SEU Upsets: >100 MEV-cm2/mg ? Single Event Upset (SEU) Immunity 1 x 1012 RAD (Si)/s ? Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse ? Latc

文件：396.42 Kbytes 頁(yè)數(shù)：9 Pages

RENESAS

瑞薩

Radiation Hardened Synchronous Counter

Description The Intersil HCTS161AMS high-reliability high-speed presettable four-bit binary synchronous counter features asynchronous reset and look-ahead carry logic. The HCTS161AMS has an active-low master reset to zero, MR. A low level at the synchronous parallel enable, SPE, disables counting

文件：115.77 Kbytes 頁(yè)數(shù)：9 Pages

INTERSIL