Dual P-Channel, Digital FET

General Description These dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especi

文件：227.13 Kbytes 頁數(shù)：8 Pages

FAIRCHILD

仙童半導(dǎo)體

Dual P-Channel, Digital FET

ONSEMI

安森美半導(dǎo)體

Dual P-Channel, Digital FET

General Description These dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especi

文件：227.13 Kbytes 頁數(shù)：8 Pages

FAIRCHILD

仙童半導(dǎo)體

雙 P 溝道，數(shù)字 FET，-25V，0.41A，1.1Ω

這些P溝道邏輯電平增強模式功率場效應(yīng)晶體管采用飛兆專有的高密度、DMOS技術(shù)生產(chǎn)。 這種密度非常高的工藝是專為最大限度地降低導(dǎo)通阻抗而定制的。 該器件特別為低電壓應(yīng)用設(shè)計，以替代雙極數(shù)字晶體管和小信號MOSFETS。 ?-25 V、-0.41 A（連續(xù)值）、-1.5 A（峰值）。\n?RDS(ON) = 1.1 Ω @ VGS = 4.5 V，\n?RDS(ON) = 1.5 Ω @ VGS= -2.7 V。 \n?電平柵極驅(qū)動要求極低，從而可在3V電路中直接運行(VGS(th)< 1.5 V)。\n?柵-源齊納二極管增強耐靜電放電(ESD)能力（>6kV人體模型）。\n?緊湊的工業(yè)標(biāo)準(zhǔn)SC70-6表面貼裝封裝。;

ONSEMI

安森美半導(dǎo)體

包裝：卷帶（TR） 類別：分立半導(dǎo)體產(chǎn)品 晶體管 - FET，MOSFET - 陣列 描述：INTEGRATED CIRCUIT

ONSEMI

安森美半導(dǎo)體