Digital FET, Dual N-Channel

General Description These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especi

文件：72.12 Kbytes 頁數(shù)：4 Pages

FAIRCHILD

仙童半導(dǎo)體

Digital FET, Dual N-Channel

General Description\nThese dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especial ■ 25 V, 0.68 A continuous, 2 A Peak.\n?? RDS(ON) = 0.6 W @ VGS = 2.7 V\n?? RDS(ON) = 0.45 W @ VGS= 4.5 V.\n■ Very low level gate drive requirements allowing direct\n?? operation in 3V circuits. VGS(th) < 1.5 V.\n■ Gate-Source Zener for ESD ruggedness.\n?? 6kV Human Body Model\n■ Replace multiple NPN;

ONSEMI

安森美半導(dǎo)體

Digital FET, Dual N-Channel

General Description These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especi

文件：72.12 Kbytes 頁數(shù)：4 Pages

FAIRCHILD

仙童半導(dǎo)體

雙 N 溝道，數(shù)字 FET，25V，0.68A，0.45Ω

這些雙N溝道邏輯電平增強(qiáng)模式場(chǎng)效應(yīng)晶體管采用飛兆半導(dǎo)體專有的高電池密度DMOS技術(shù)生產(chǎn)。 這種密度非常高的工藝是專為最大限度地降低導(dǎo)通阻抗而定制的。 該器件特別為低電壓應(yīng)用設(shè)計(jì)，以替代數(shù)字晶體管。 由于不需要偏置電阻，該N溝道FET能替代一些具有不同偏置電阻的數(shù)字晶體管，如IMHxA系列。 ?-25V、-0.68A（連續(xù)值）、-2A（峰值） \n?RDS(ON) = 0.6 Ω @ VGS = 2.7 V\n?RDS(ON) = 0.45 Ω @ VGS= 4.5 V\n?柵極驅(qū)動(dòng)電平要求極低，從而可在3V電路中直接運(yùn)行。 VGS(th) < 1.5V。\n?柵-源齊納二極管增強(qiáng)耐靜電放電(ESD)能力。 >6kV人體模型\n?用一個(gè)DMOS FET替代多個(gè)NPN數(shù)字晶體管（IMHxA系列）;

ONSEMI

安森美半導(dǎo)體