FC8080中文資料RF + BB SoC for T-DMB數(shù)據(jù)手冊Renesas規(guī)格書

描述 Description

The FCI FC8080 chip is a highly integrated device for terrestrial digital multimedia Broadcasting. FC8080 has all of the performance needed to enable the full range of T-DMB application. It consists of two main blocks, RF tuner and channel decoder.
RF block supports single-band (Band-III). It is a highly integrated component working with a single 1.2V power supply. Because direct-conversion architecture is used in RF block, additional components such as bulky IF SAW filter and other IF matching components are no longer required. For the direct-conversion, it has low noise fractional-N type frequency synthesizer and VCO. RF block contains LNA, down-conversion mixer, channel selection filter (CSF), and LO distribution network for Band-3.
Baseband block is a integrated circuit provides channel decoder for Digital Multimedia Broadcasting(DMB) signals based on ETS 300 401 (EUREKA-147). It is also in compliance with the function of Korea DAB/DMB (TTAS.KO -07.0024 and TTAS.KO-07.0026) standard. It contains 10-bit Analog to Digital Converter (ADC) for IF input, OFDM demodulator, Reed Solomon decoder and convolutional de-interleaver for providing forward error correcting. For Audio data, It uses MPEG I/II Layer II (MUSICAM) algorithm. It provides EBI2 LCD Interface of Qualcomm QSC series modem chip, SPI and I2C as a HOST interface. When it is used I2C as host interface, serial TS interface is supported for data transmission also.

特性 Features

? Highly integrated digital device for DAB receiver (Eureka 147)
? Korea DAB/DMB (TTAS.KO -07.0024 and TTAS.KO-07.0026) standard compliant
? DAB OFDM channel demodulator and decoder
? Fully integrated, supports all DAB functions and modes (I, II, III and IV)
? Mode Detection (AMD)
? Full data rate of 1.8Mbit can be decoded
? Automatic frame and time synchronization and fast channel re-acquisition
? Digital AGC with a wide gain control range
? Demodulation and decoding of up to 64 sub-channels (UEP/EEP) TII decoder
? Automatic multiplex re-configuration

? Integrated high-density SRAM supporting time and frequency de-interleaving
? Simple memory concept. Do not require external memory for DAB operation

? Interfaces
? Parallel Host Interface
? 3-bit control pins, 4-bit data bus, it is compatible with Qualcomm QSC series modem chip.

? Serial Host Interface
? SPI : up to 38.4MHz
? I2C : up to 1.0MHz for control and up to 38.4MHz serial TS interface for data

? Support max. 4 services (audio, video and data stream) of Data service
? MPEG-2 Serial-TS output
? Various TS clock : 1.024 ~ 38.4MHz

? Be able to decode 2 video data with RS encoded stream
? Automatically internal hardware reset drive without external reset pin

應用 Application

·RF + BB SoC for T-DMB