絲印：F11；DIGITAL TRANSISTOR

Features 1) Built-In Biasing Resistors, R1 = R2 = 10kΩ 2) Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistors (see inner circuit) . 3) Only the on/off conditions need to be set for operation, making the circuit design e

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ROHM

羅姆

絲?。?strong>F11；Package：SMT3；-500mA / -50V Digital transistors (with built-in resistors)

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ROHM

羅姆

絲?。?a target="_blank" title="Marking" href="/f112/marking.html">F112；Package：SOIC；DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of t

文件：566.64 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/f112/marking.html">F112；Package：SOIC；DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of t

文件：566.64 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/f112/marking.html">F112；Package：SOIC；DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of t

文件：566.64 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

絲印：F11NM80；Package：TO-220FP；N-channel 800 V, 0.35 Ω, 11 A MDmesh? Power MOSFET in D2PAK, TO-220FP, I2PAK, TO-220, TO-247

Features ■ Low input capacitance and gate charge ■ Low gate input resistance ■ Best RDS(on)*Qg in the industry Applications ■ Switching applications Description These N-channel Power MOSFETs are developed using STMicroelectronics' revolutionary MDmesh? technology, which associates th

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STMICROELECTRONICS

意法半導(dǎo)體

絲印：F1170；Package：SMAFlat；170 V, 1 A power Schottky rectifier

Features ? Negligible switching losses ? High junction temperature capability ? Very small conduction losses ? Low leakage current ? Avalanche rated ? ECOPACK2 component

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STMICROELECTRONICS

意法半導(dǎo)體

絲?。?a target="_blank" title="Marking" href="/f1170/marking.html">F1170；Package：SMAflat；Power Schottky rectifier

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STMICROELECTRONICS

意法半導(dǎo)體

This document describes the specifications for the IDTF1178 Zero-DistortionTM RF to IF Downconverting Dual Mixer.

GENERAL DESCRIPTION This document describes the specifications for the IDTF1178 Zero-DistortionTM RF to IF Downconverting Dual Mixer. This device is part of a series of mixers offered with high side and/or low side injection options for all UTRA bands. See the Part# Matrix for pin compatible

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RENESAS

瑞薩

RF to IF Dual Downconverting Mixer

FEATURES ? Dual Path for Diversity Systems ? Ideal for Multi-Carrier Systems ? 8.9 dB Gain ? Ultra linear +43 dBm IP3O ? Low NF

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RENESAS

瑞薩