絲?。?strong>F109；Package：SOIC；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the

文件：904.8 Kbytes 頁數(shù)：15 Pages

TI

德州儀器

絲?。?strong>F109；Package：SOIC；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the

文件：904.8 Kbytes 頁數(shù)：15 Pages

TI

德州儀器

絲印：F109；Package：SOIC；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the

文件：904.8 Kbytes 頁數(shù)：15 Pages

TI

德州儀器

PNP Epitaxial Planar Silicon Composite Transistor Switching Applications

Switching Applications Features ? On-chip bias resistors (R1=22k?, R2=22k?) ? Composite type with 2 transistors contained in the CP package currently in use, improving the mounting efficiency greatly. ? The FC109 is formed with two chips, being equivalent to the 2SA1342, placed in one package.

文件：44.6 Kbytes 頁數(shù)：2 Pages

SANYO

三洋

SOT23 SILICON PLANAR VARIABLE CAPACITANCE DIODE

SOT23 SILICON PLANAR VARIABLE CAPACITANCE DIODE

文件：35.54 Kbytes 頁數(shù)：1 Pages

ZETEX

Broadband Frequency Doubler, 10 - 4800 MHz Output

文件：216.89 Kbytes 頁數(shù)：3 Pages

MACOM