CMOS Dual 2 Wide 2 Input AND-OR-INVERT Gate

Description CD4085BMS contains a pair of AND-OR-INVERT gates, each consisting of two 2 input AND gates driving a 3 input NOR gate. Individual inhibit controls are provided for both A-O-I gates.. The CD4085BMS is supplied in these 14 lead outline packages: Braze Seal DIP H4H Frit Seal DI

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INTERSIL

CMOS DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATE

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TI

德州儀器

CMOS Dual 2 Wide 2 Input AND-OR-INVERT Gate

Description\nCD4085BMS contains a pair of AND-OR-INVERT gates, each consisting of two 2 input AND gates driving a 3 input NOR gate. Individual inhibit controls are provided for both A-O-I gates.. The CD4085BMS is supplied in these 14 lead outline packages:Braze Seal DIP H4H\nFrit Seal DIP H1B\nCeram ? High Voltage Type (20V Rating)\n? Medium Speed Operation\n- tPHL = 90ns\n- tPLH = 125ns (Typ.) at 10V\n? Individual Inhibit Controls\n? 5V, 10V and 15V Parametric Ratings\n? Standardized Symmetrical Output Characteristics\n? 100% Tested for Quiescent Current at 20V\n? Maximum Input Current of ;

Renesas

瑞薩

2路2輸入與或非門

The CD4085 is a dual 2-input And-Or-Invert Gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected t ? Wide supply voltage range from 3V to 15V\n? Fully static operation\n? 5V, 10V, and 15V parametric ratings\n? Standardized symmetrical output characteristics\n? Specified from -40℃ to +105℃\n? Packaging information: DIP14/SOP14/TSSOP14;

I-CORE

中微愛(ài)芯

CMOS DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATE

TI

德州儀器

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

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TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd4085be/marking.html">CD4085BE；Package：PDIP；CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

文件：938.91 Kbytes 頁(yè)數(shù)：20 Pages

TI

德州儀器

絲印：CD4085BE；Package：PDIP；CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

文件：938.91 Kbytes 頁(yè)數(shù)：20 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd4085bf/marking.html">CD4085BF；Package：CDIP；CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

文件：938.91 Kbytes 頁(yè)數(shù)：20 Pages

TI

德州儀器

絲印：CD4085BF；Package：CDIP；CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

文件：938.91 Kbytes 頁(yè)數(shù)：20 Pages

TI

德州儀器