Cyclone FPGA Family Data Sheet

Introduction The Cyclone? field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

文件：1.35316 Mbytes 頁數(shù)：104 Pages

ALTERA

阿爾特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone? field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

文件：1.38683 Mbytes 頁數(shù)：106 Pages

ALTERA

阿爾特

Cyclone FPGA Family

文件：1.14233 Mbytes 頁數(shù)：94 Pages

ALTERA

阿爾特

Cyclone FPGA Family

文件：1.3576 Mbytes 頁數(shù)：106 Pages

ALTERA

阿爾特