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首頁 >EP1C20>規(guī)格書列表

型號(hào)	下載訂購	功能描述	制造商上傳企業(yè)	LOGO
EP1C20F100C7ES	文件：1.35316 Mbytes Page：104 Pages	Cyclone FPGA Family Data Sheet Introduction The Cyclone? field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) 文件：1.35316 Mbytes 頁數(shù)：104 Pages	ALTERA 阿爾特	ALTERA
EP1C20F100C8ES	文件：1.35316 Mbytes Page：104 Pages	Cyclone FPGA Family Data Sheet Introduction The Cyclone? field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) 文件：1.35316 Mbytes 頁數(shù)：104 Pages	ALTERA 阿爾特	ALTERA
EP1C20F100I6ES	文件：1.35316 Mbytes Page：104 Pages	Cyclone FPGA Family Data Sheet Introduction The Cyclone? field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) 文件：1.35316 Mbytes 頁數(shù)：104 Pages	ALTERA 阿爾特	ALTERA
EP1C20F100I7ES	文件：1.35316 Mbytes Page：104 Pages	Cyclone FPGA Family Data Sheet Introduction The Cyclone? field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) 文件：1.35316 Mbytes 頁數(shù)：104 Pages	ALTERA 阿爾特	ALTERA
EP1C20F100I8ES	文件：1.35316 Mbytes Page：104 Pages	Cyclone FPGA Family Data Sheet Introduction The Cyclone? field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) 文件：1.35316 Mbytes 頁數(shù)：104 Pages	ALTERA 阿爾特	ALTERA
EP1C20F144C6ES	文件：1.35316 Mbytes Page：104 Pages	Cyclone FPGA Family Data Sheet Introduction The Cyclone? field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) 文件：1.35316 Mbytes 頁數(shù)：104 Pages	ALTERA 阿爾特	ALTERA
EP1C20F144C7ES	文件：1.35316 Mbytes Page：104 Pages	Cyclone FPGA Family Data Sheet Introduction The Cyclone? field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) 文件：1.35316 Mbytes 頁數(shù)：104 Pages	ALTERA 阿爾特	ALTERA
EP1C20F144C8ES	文件：1.35316 Mbytes Page：104 Pages	Cyclone FPGA Family Data Sheet Introduction The Cyclone? field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) 文件：1.35316 Mbytes 頁數(shù)：104 Pages	ALTERA 阿爾特	ALTERA
EP1C20F144I6ES	文件：1.35316 Mbytes Page：104 Pages	Cyclone FPGA Family Data Sheet Introduction The Cyclone? field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) 文件：1.35316 Mbytes 頁數(shù)：104 Pages	ALTERA 阿爾特	ALTERA
EP1C20F144I7ES	文件：1.35316 Mbytes Page：104 Pages	Cyclone FPGA Family Data Sheet Introduction The Cyclone? field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) 文件：1.35316 Mbytes 頁數(shù)：104 Pages	ALTERA 阿爾特	ALTERA

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詳細(xì)參數(shù)

型號(hào)：
EP1C20
制造商：
ALTERA
制造商全稱：
Altera Corporation
功能描述：
1. Enhanced Configuration Devices(EPC4, EPC8, and EPC16) Data Sheet

供應(yīng)商	型號(hào)	品牌	批號(hào)	封裝	庫存	備注	價(jià)格
諦輝(北京/上海/青島 )電子科技有限公司	EP1C20F324I7	ALTERA	25+	CDIP16	18000	原廠直接發(fā)貨進(jìn)口原裝	詢價(jià)
深圳市益百分電子有限公司	EP1C20F400C8N	ALTERA	07+	BGA	2500	全新原裝進(jìn)口自己庫存優(yōu)勢	詢價(jià)
深圳市福安甌科技有限公司	EP1C20F400C8N	ALTERA	25+	BGA	500		詢價(jià)
芯有半導(dǎo)體（深圳）有限公司	EP1C20F324C6	ALTERA	05+	原廠原裝	4269	只做全新原裝真實(shí)現(xiàn)貨供應(yīng)	詢價(jià)
深圳市凌旭科技有限公司	EP1C20F400C7N	ALTERA	2016+	BGA	3000	公司只做原裝,假一賠十,可開17%增值稅發(fā)票!	詢價(jià)
深圳市勤思達(dá)科技有限公司	EP1C20F324C7N	ALTERA	09+	BGA	5500	原裝無鉛,優(yōu)勢熱賣	詢價(jià)
深圳市毅創(chuàng)騰電子科技有限公司	EP1C20F400C8N	ALTERA	23+	BGA400	5500	現(xiàn)貨,全新原裝	詢價(jià)
深圳市歐立現(xiàn)代科技有限公司	EP1C20F400I7N	alterA	24+		12	原裝現(xiàn)貨,可開13%稅票	詢價(jià)
深圳市卓越微芯電子有限公司	EP1C20F400I7N	ALTERA	25+	BGA	550	百分百原裝正品真實(shí)公司現(xiàn)貨庫存本公司只做原裝可	詢價(jià)
齊創(chuàng)科技(上海,北京,青島)有限公司	EP1C20F400C6N	ALTERA	23+	QFP	5000	原裝正品,假一罰十	詢價(jià)

更多EP1C20供應(yīng)商更新時(shí)間2026-1-20 16:48:00

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