絲?。?a target="_blank" title="Marking" href="/b10/marking.html">B10；Package：EMT6；General purpose (dual digital transistors)

Features 1) Two DTA123J chips in a EMT or UMT or SMT package. 2) Mounting possible with EMT3 or UMT3 or SMT3 automatic mounting machines. 3) Transistor elements are independent, eliminating interference. 4) Mounting cost and area can be cut in half. Application INVERTER, INTERFACE, DRIVE

文件：73.58 Kbytes 頁數(shù)：3 Pages

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絲?。?a target="_blank" title="Marking" href="/b10/marking.html">B10；Package：EMT6；PNP -100mA -50V Complex Digital Transistors

lFeatures 1) Built-In Biasing Resistors. 2) Two DTA123J chips in one package. 3) Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistors (see inner circuit). 4) The bias resistors consist of thin-film resistors with complete isolat

文件：1.50031 Mbytes 頁數(shù)：10 Pages

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絲?。?a target="_blank" title="Marking" href="/b11/marking.html">B11；Package：EMT6；General purpose Dual digital transistors

Features 1) Two DTA114E chips in a EMT or UMT or SMT package. 2) Mounting possible with EMT3 or UMT3 or SMT3 automatic mounting machines. 3) Transistor elements are independent, eliminating interference. 4) Mounting cost and area can be cut in half.

文件：1.56923 Mbytes 頁數(shù)：11 Pages

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絲?。?a target="_blank" title="Marking" href="/b11/marking.html">B11；Package：EMT6；General purpose (dual digital transistors)

Features 1) Two DTA114E chips in a EMT or UMT or SMT package. 2) Mounting possible with EMT3 or UMT3 or SMT3 automatic mounting machines. 3) Transistor elements are independent, eliminating interference. 4) Mounting cost and area can be cut in half.

文件：74.33 Kbytes 頁數(shù)：3 Pages

ROHM

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絲?。?a target="_blank" title="Marking" href="/b11/marking.html">B11；Package：EMT6；PNP -100mA -50V Complex Digital Transistors

Features 1) Two DTA114E chips in a EMT or UMT or SMT package. 2) Mounting possible with EMT3 or UMT3 or SMT3 automatic mounting machines. 3) Transistor elements are independent, eliminating interference. 4) Mounting cost and area can be cut in half.

文件：486.32 Kbytes 頁數(shù)：8 Pages

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Dual N??hannel Logic Level Enhancement Mode Field Effect Transistor

Product Summary: BVDSS 30V RDSON (MAX.) 11mΩ ID 12A UIS, Rg 100 Tested Pb‐Free Lead Plating & Halogen Free

文件：202.07 Kbytes 頁數(shù)：5 Pages

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絲印：B11；Package：SOT-563；General purpose (Dual digital transistors)

lFeatures 1)Two DTA114E chips in a EMT6 package. 2)Mounting possible with EMT3 automatic mounting machines. 3)Transistor elements are independent, eliminating interference. 4)Mounting cost and area can be cut in half. lApplication INVERTER, INTERFACE, DRIVER

文件：1.28452 Mbytes 頁數(shù)：7 Pages

ROHM

羅姆

General purpose (Dual digital transistors)

lFeatures 1)Two DTA114E chips in a EMT6 package. 2)Mounting possible with EMT3 automatic mounting machines. 3)Transistor elements are independent, eliminating interference. 4)Mounting cost and area can be cut in half. lApplication INVERTER, INTERFACE, DRIVER

文件：1.28452 Mbytes 頁數(shù)：7 Pages

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Dual Asymmetric N??hannel Logic Level Enhancement Mode Field Effect Transistor

Product Summary: N‐CH‐Q1 N‐CH‐Q2 BVDSS 30V 30V RDSON (MAX.) 15.5mΩ 12.5mΩ ID 9A 10A UIS, Rg 100 Tested Pb‐Free Lead Plating & Halogen Free

文件：220.41 Kbytes 頁數(shù)：8 Pages

EXCELLIANCE

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Dual N??hannel Logic Level Enhancement Mode Field Effect Transistor

Product Summary: N‐CH‐Q1 N‐CH‐Q2 BVDSS 30V 30V RDSON (MAX.) 12mΩ 17mΩ ID 12A 10A UIS, Rg 100 Tested Pb‐Free Lead Plating & Halogen Free

文件：207.84 Kbytes 頁數(shù)：8 Pages

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杰力科技