Horizontal genlock, 4 F sc

General Description\nThe EL4584C is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multi ple of the TV Horizontal scan rate 36 MHz, general purpose PLL\n4FSCbased timing (use the EL4585 for 8 FSC)\nCompatible w/EL4583 Sync Separator\nVCXO, Xtal, or LC tank oscillator\nk2 ns jitter (VCXO)\nUser controlled PLL capture and lock\nCompatible with NTSC and PAL TV formats\n8 pre-programmed TV scan rate clock divisors\nSelectabl;

Renesas

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Horizontal Genlock/ 4FSC

Renesas

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Package：16-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR） 類別：集成電路（IC） 時(shí)鐘發(fā)生器，PLL，頻率合成器 描述：IC PLL VIDEO GP 36MHZ 16-SOIC

Renesas Electronics America Inc

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：管件 類別：集成電路（IC） 時(shí)鐘發(fā)生器，PLL，頻率合成器 描述：IC GENLOCK HORZ 4FSC 16-SOIC

Renesas Electronics America Inc

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR） 類別：集成電路（IC） 時(shí)鐘發(fā)生器，PLL，頻率合成器 描述：IC PLL VIDEO GP 36MHZ 16-SOIC

Renesas Electronics America Inc