EBE21AE8ACFA中文資料爾必達(dá)數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

2GB Registered DDR2 SDRAM DIMM

特性 Features

? Double-data-rate architecture; two data transfers per clock cycle

? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture

? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at

the receiver

? DQS is edge-aligned with data for READs; center aligned with data for WRITEs

? Differential clock inputs (CK and /CK)

? DLL aligns DQ and DQS transitions with CK transitions

? Commands entered on each positive CK edge; data referenced to both edges of DQS

? Data mask (DM) for write data

? Posted /CAS by programmable additive latency for better command and data bus efficiency

? Off-Chip-Driver Impedance Adjustment and On-Die Termination for better signal quality

? /DQS can be disabled for single-ended Data Strobe operation

? 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2K bits EEPROM) for

Presence Detect (PD)