EURO BLOCKS TS & EB SERIES

文件：159.33 Kbytes 頁(yè)數(shù)：1 Pages

ADAM-TECH

亞當(dāng)科技

1GB Registered DDR2 SDRAM DIMM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver ?

文件：210.98 Kbytes 頁(yè)數(shù)：23 Pages

ELPIDA

爾必達(dá)

1GB Registered DDR2 SDRAM DIMM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver ?

文件：210.98 Kbytes 頁(yè)數(shù)：23 Pages

ELPIDA

爾必達(dá)

1GB Registered DDR2 SDRAM DIMM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver ?

文件：210.98 Kbytes 頁(yè)數(shù)：23 Pages

ELPIDA

爾必達(dá)

1GB Registered DDR2 SDRAM DIMM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver ?

文件：210.98 Kbytes 頁(yè)數(shù)：23 Pages

ELPIDA

爾必達(dá)

1GB Registered DDR2 SDRAM DIMM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver ?

文件：240.93 Kbytes 頁(yè)數(shù)：28 Pages

ELPIDA

爾必達(dá)

1GB Registered DDR2 SDRAM DIMM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver ?

文件：240.93 Kbytes 頁(yè)數(shù)：28 Pages

ELPIDA

爾必達(dá)

1GB Registered DDR2 SDRAM DIMM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver ?

文件：242.14 Kbytes 頁(yè)數(shù)：27 Pages

ELPIDA

爾必達(dá)

1GB Registered DDR2 SDRAM DIMM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver ?

文件：242.14 Kbytes 頁(yè)數(shù)：27 Pages

ELPIDA

爾必達(dá)

1GB Registered DDR2 SDRAM DIMM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver ?

文件：242.14 Kbytes 頁(yè)數(shù)：27 Pages

ELPIDA

爾必達(dá)