絲印：EBE；Package：8Ld2x3DFN；LDO with Low ISUPPLY, High PSRR

LDO with Low ISUPPLY, High PSRR ISL9001A is a high performance Low Dropout linear regulator capable of sourcing 300mA current. It has a low standby current and high-PSRR and is stable with output capacitance of 1μF to 10μF with ESR of up to 200mΩ. Features ? 300mA high performance LDO ? Excell

文件：624.42 Kbytes 頁(yè)數(shù)：12 Pages

RENESAS

瑞薩

絲?。?strong>EBE；Package：SMC；5000 W TVS in SMC

Features ? Peak pulse power: – 5000 W (10/1000 μs) – up to 48 kW (8/20 μs) ? Stand-off voltage range from 5 V to 100 V ? Unidirectional type ? Low leakage current: 0.2 μA at 25 °C ? Operating Tj max: 175 °C ? JEDEC registered package outline ? Resin meets UL94, V0 ? Lead finishing: matte

文件：484.31 Kbytes 頁(yè)數(shù)：12 Pages

STMICROELECTRONICS

意法半導(dǎo)體

絲印：EBEY；Package：SMA；Automotive 5000 W TVS in SMC

Features ? AEC-Q101 qualified ? Peak pulse power: – 5000 W (10/1000 μs) – up to 48 kW (8/20 μs) ? Stand-off voltage range from 5 V to 100 V ? Unidirectional and bidirectional types ? Low leakage current: 0.2 μA at 25 °C ? Operating Tj max: 175 °C ? JEDEC registered package outline ? Lead

文件：1.88727 Mbytes 頁(yè)數(shù)：15 Pages

STMICROELECTRONICS

意法半導(dǎo)體

絲印：EBEY；Package：SMA；Automotive 5000 W TVS in SMC

Features ? AEC-Q101 qualified ? Peak pulse power: – 5000 W (10/1000 μs) – up to 48 kW (8/20 μs) ? Stand-off voltage range from 5 V to 100 V ? Unidirectional and bidirectional types ? Low leakage current: 0.2 μA at 25 °C ? Operating Tj max: 175 °C ? JEDEC registered package outline ? Lead

文件：1.88727 Mbytes 頁(yè)數(shù)：15 Pages

STMICROELECTRONICS

意法半導(dǎo)體

1GB Registered DDR2 SDRAM DIMM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver ?

文件：210.98 Kbytes 頁(yè)數(shù)：23 Pages

ELPIDA

爾必達(dá)

1GB Registered DDR2 SDRAM DIMM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver ?

文件：210.98 Kbytes 頁(yè)數(shù)：23 Pages

ELPIDA

爾必達(dá)

1GB Registered DDR2 SDRAM DIMM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver ?

文件：210.98 Kbytes 頁(yè)數(shù)：23 Pages

ELPIDA

爾必達(dá)

1GB Registered DDR2 SDRAM DIMM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver ?

文件：210.98 Kbytes 頁(yè)數(shù)：23 Pages

ELPIDA

爾必達(dá)

1GB Registered DDR2 SDRAM DIMM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver ?

文件：240.93 Kbytes 頁(yè)數(shù)：28 Pages

ELPIDA

爾必達(dá)

1GB Registered DDR2 SDRAM DIMM

Features ? Double-data-rate architecture; two data transfers per clock cycle ? The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver ?

文件：240.93 Kbytes 頁(yè)數(shù)：28 Pages

ELPIDA

爾必達(dá)