2GB Registered DDR SDRAM DIMM

Description The EBD21RD4ABNA is a 256M words × 72 bits, 2 bank Double Data Rate (DDR) SDRAM Module, mounted 36 pieces of DDR SDRAM sealed in TCP package. Read and write operations are performed at the cross points of the CK and the /CK. This high speed data transfer is realized by the 2-bit prefe

文件：177.49 Kbytes 頁數(shù)：19 Pages

ELPIDA

爾必達

2GB Registered DDR SDRAM DIMM

Description The EBD21RD4ABNA is a 256M words × 72 bits, 2 bank Double Data Rate (DDR) SDRAM Module, mounted 36 pieces of DDR SDRAM sealed in TCP package. Read and write operations are performed at the cross points of the CK and the /CK. This high speed data transfer is realized by the 2-bit prefe

文件：177.49 Kbytes 頁數(shù)：19 Pages

ELPIDA

爾必達

2GB Registered DDR SDRAM DIMM

Description The EBD21RD4ABNA is a 256M words × 72 bits, 2 bank Double Data Rate (DDR) SDRAM Module, mounted 36 pieces of DDR SDRAM sealed in TCP package. Read and write operations are performed at the cross points of the CK and the /CK. This high speed data transfer is realized by the 2-bit prefe

文件：177.49 Kbytes 頁數(shù)：19 Pages

ELPIDA

爾必達

2GB Registered DDR SDRAM DIMM

Description The EBD21RD4ABNA is a 256M words × 72 bits, 2 bank Double Data Rate (DDR) SDRAM Module, mounted 36 pieces of DDR SDRAM sealed in TCP package. Read and write operations are performed at the cross points of the CK and the /CK. This high speed data transfer is realized by the 2-bit prefe

文件：177.49 Kbytes 頁數(shù)：19 Pages

ELPIDA

爾必達

2GB Registered DDR SDRAM DIMM

Micron

美光

2GB Registered DDR SDRAM DIMM

Description\nThe EBD21RD4ABNA is a 256M words × 72 bits, 2 bank Double Data Rate (DDR) SDRAM Module, mounted 36 pieces of DDR SDRAM sealed in TCP package. Read and write operations are performed at the cross points of the CK and the /CK. This high speed data transfer is realized by the 2-bit prefetc ? 184-pin socket type dual in line memory module (DIMM)\n?? - PCB height: 30.48mm\n?? - Lead pitch: 1.27mm\n? 2.5V power supply\n? Data rate: 266Mbps/200Mbps (max.)\n? 2.5 V (SSTL_2 compatible) I/O\n? Double Data Rate architecture; two data transfers per clock cycle\n? Bi-directional, data strobe (D;

Micron

美光