Implementing Viterbi Decoders Using the VSL Instruction on DSP Families

24-Bit Digital Signal Processor The DSP56309 is a member of the DSP56300 core family of programmable CMOS DSPs. The DSP56300 core includes a barrel shifter, 24-bit addressing, an instruction cache, and direct memory access (DMA). The DSP56309 offers 100 MMACS at 3.0–3.6 V using an inter

文件：1.08544 Mbytes 頁數(shù)：108 Pages

FREESCALEFreescale Semiconductor, Inc

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DSP56603EVM Evaluation Module

FEATURES ? 16-bit DSP56603 Digital Signal Processor – High Performance DSP56600 Core ? 60 Million Instructions Per Second (MIPS) with a 60 MHz clock (at 2.7 volts) ? Object-code compatible with the DSP56000 and DSP56300 cores ? Highly parallel instruction set ? Fully pipelined 16 ′ 16-bit

文件：321.35 Kbytes 頁數(shù)：8 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC

FEATURES RISC M?CORE MCU ? 32-bit load/store RISC architecture ? Fixed 16-bit instruction length ? 16-entry 32-bit general-purpose register file ? 32-bit internal address and data buses ? Efficient four-stage, fully interlocked execution pipeline ? Single-cycle execution for most instructio

文件：1.27961 Mbytes 頁數(shù)：76 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC

FEATURES RISC M?CORE MCU ? 32-bit load/store RISC architecture ? Fixed 16-bit instruction length ? 16-entry 32-bit general-purpose register file ? 32-bit internal address and data buses ? Efficient four-stage, fully interlocked execution pipeline ? Single-cycle execution for most instructio

文件：1.27961 Mbytes 頁數(shù)：76 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR

FEATURES RISC M￥CORE MCU ￥ 32-bit load/store RISC architecture ￥ Fixed 16-bit instruction length ￥ 16-entry 32-bit general-purpose register file ￥ 32-bit internal address and data buses ￥ Efficient four-stage, fully interlocked execution pipeline ￥ Single-cycle execution for most instructio

文件：1.13755 Mbytes 頁數(shù)：76 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR

FEATURES RISC M￥CORE MCU ￥ 32-bit load/store RISC architecture ￥ Fixed 16-bit instruction length ￥ 16-entry 32-bit general-purpose register file ￥ 32-bit internal address and data buses ￥ Efficient four-stage, fully interlocked execution pipeline ￥ Single-cycle execution for most instructio

文件：1.13755 Mbytes 頁數(shù)：76 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC

FEATURES RISC M?CORE MCU ? 32-bit load/store RISC architecture ? Fixed 16-bit instruction length ? 16-entry 32-bit general-purpose register file ? 32-bit internal address and data buses ? Efficient four-stage, fully interlocked execution pipeline ? Single-cycle execution for most instructio

文件：1.27961 Mbytes 頁數(shù)：76 Pages

恩XP

16-BIT DIGITAL SIGNAL PROCESSOR

文件：247.9 Kbytes 頁數(shù)：4 Pages

FREESCALEFreescale Semiconductor, Inc

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INTERGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC

文件：239.95 Kbytes 頁數(shù)：4 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導(dǎo)體

INTERGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC

文件：239.95 Kbytes 頁數(shù)：4 Pages

FREESCALEFreescale Semiconductor, Inc

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